Semiconductor device manufacturing: process – Chemical etching
Reexamination Certificate
2006-03-09
2010-02-16
Nguyen, Ha Tran T (Department: 2829)
Semiconductor device manufacturing: process
Chemical etching
C438S725000, C438S736000, C257SE21020
Reexamination Certificate
active
07662718
ABSTRACT:
Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.
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International Search Report dated Jul. 20, 2007 for counterpart International Application No. PCT/US2007/005639.
Abatchev Mirzafer K.
Subramanian Krupakar Murali
Zhou Baosuo
Knobbe Martens Olson & Bear LLP
Micro)n Technology, Inc.
Nguyen Ha Tran T
Whalen Daniel
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