Trim correction circuit with temperature coefficient compensatio

Details Trim correction circuit with temperature coefficient compensatio Trim correction circuit with temperature coefficient compensatio

1991-11-20

1993-04-06

Sikes, William L.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307310, 330256, G06G 710, H03F 345

Patent

active

052006549

ABSTRACT:
An op amp bias system that provides input offset voltage trim current with minimum offset thermal drift. The bias system includes a bias generator that provides bias current to the op amp and correction circuitry responsive to the bias current for providing an input offset trim current that compensates for offset drift error with changes in temperature.

REFERENCES:
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patent: 4734594 (1988-03-01), Nelson
patent: 4853647 (1989-08-01), Low et al.
patent: 5045806 (1991-09-01), Yan
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Scott Wurcer; A 3Nv/.sqroot.Hz, DC Precise, JEFT Operational Amplifier; Analog Devices Semiconductor;
Otto H. Schede, Jr.; Advances in BIMOS Integrated Circuits; RCA Review vol. 39, Jun. 1978; pp. 250-277.
M. A. Polinsky et al.; CMOS-Bipolar Monolithic Integrated-Circuit Technology; RCA Solid State Division; Somerville, NJ 08876; pp. 229-231.
Yannis P. Tsividis; A CMOS Voltage Reference; IEEE Journal of Solid State Circuits, vol. SC-13, No. 6; Dec. 1978; pp. 774-778.
A. Paul Brokaw et al.; THPM 12.6; A Fast, High-Precision Laser-Trimmed FET Input Operational Amplifier; ISSCC 74./Feb. 14, 1974; pp. 142-143 & 244.
Ronald W. Russell et al.; THPM 12.5; Ion Implanted JFET-Bipolar Monolithic Analog Circuits; ISSCC 74/Feb. 14, 1974; pp. 140-141 & 243.
Eric Vittoz et al.; CMOS Analog Integrated Circuits Based on Weak Inversion Operation; IEEE Journal of Solid-State Circuits; vol. SC-12, No. 3, Jun. 1977; pp. 224-231.

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