Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-03-14
2004-08-31
Phung, Anh (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185330, C365S189090
Reexamination Certificate
active
06785163
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a flash memory, and more particularly to a trim circuit and method for tuning a current level of a reference cell in a flash memory.
BACKGROUND OF THE INVENTION
During the operation of reading data out from a flash memory, the charge sensing thereof is of the most importance and by which the data read-out operation requires fast, accurate and reliable determination of the level of each selected memory cell under the direct connection of the memory cell to a sense amplifier.
FIG. 1
shows a schematic diagram of reading out of data from a flash memory array, in which the memory cell
12
to be read is selected from the memory array and is connected to a sense amplifier
16
that is further connected with a reference cell or dummy cell
14
so as to compare the cell current from the memory cell
12
and the reference current from the reference cell
14
to thereby determine the sense signal at the output of the sense amplifier
16
. Both the memory cell
12
and reference cell
14
are flash cells, and the sensing of data read-out is based on the threshold voltage V
t,Ref
, where V
t,Ref
has a designed or predetermined level, of the reference cell
14
that is biased to conducts a current proportional to its threshold voltage V
t,Ref
. During the tracking operation of this memory, the word line signal voltage V
WL
is applied to the gate of the memory cell
12
whose source is grounded and whose drain is accessed. In this mode, the memory cell
12
conducts a cell current I
Cell
proportional to its threshold voltage V
t,Cell
, and in the reference cell
14
the word line signal voltage V
WL
is applied directly to the gate of the reference cell
14
. Therefore, if the current I
Cell
flowing through the memory cell
12
is larger than the reference current I
Ref
of the reference cell
14
, i.e., I
Cell
>I
Ref
, then the threshold voltage V
t,Cell
of the memory cell
12
can be determined smaller than the threshold voltage V
t,Ref
of the reference cell
14
, i.e., V
t,Cell
<V
t,Ref
. Read-out of the data is accomplished by comparing the current I
Cell
flowing through the memory cell
12
with the current I
Ref
flowing through the reference cell
14
, and these currents are sensed by connecting the drains of the memory cell
12
and reference cell
14
to an active load, such as the differential amplifier
16
shown in FIG.
1
. If it is determined I
Cell
>I
Ref
, the sense amplifier
16
outputs logic 1, otherwise it outputs logic 0. The sensing operation for data read-out described herewith is also employed in the programming operation of the memory. During the operation of programming, sensing is used to verify if the memory cell
12
has been programmed to the desired level.
FIG. 2
shows an alternative circuit, which is based on the same principle and operation as in
FIG. 1
, only that the reference cell
18
is a MOS transistor, instead of a flash cell, and the word line signal voltage V
WL
is modified by a gate coupling ratio (GCR) before it is applied to the gate of the reference cell
18
.
FIG. 3
further shows a circuit to generate the GCR for the reference cell
20
by dividing the word line signal voltage V
WL
by a voltage divider
202
to produce a proper bias voltage to the MOS transistor
201
of the reference cell
20
.
In a flash memory, a stable reference cell and thereby the reference current thereof are desired to assure that the memory cell is programmed to the desired level during the programming procedure and the level of the memory cell is accurately sensed and determined during the reading procedure. However, the operation of the memory circuit and the manufacturing process of the memory circuit may result in current variations. For example, power supply disturbance can cause voltage variation and consequently the current level variation of the reference cell is occurred, and manufacturing process variation can cause the size of the reference cell or the GCR of the memory cell changed and, as a result, the designed current level of the reference cell drifting or changed to the extent that the circuit does not work. Therefore, a tuning circuit is necessary to adjust the current level of the reference cell in the chip testing phase. Nevertheless neither of the circuits shown in FIG.
1
and
FIG. 2
has the ability to dynamically and accurately adjust the current level of the reference cell.
FIG. 4
shows an improved circuit that introduces a resistor network
223
into its reference cell
22
to connect the voltage divider
222
for biasing the MOS transistor
221
. The resistor network
223
includes a plurality of resistors connected in series and parallel, and each of the resistors is controlled by the flash cell connected in series with it to determine whether it is connected to the other elements and thus is effective to the circuit. For instance, resistor
224
is controlled by the flash cell
225
, and the latter serves as a switch to determine if the resistor
224
is connected to the voltage divider
222
. Those flash cells in the resistor network
223
are programmed by a programming circuit
24
, and they can be only programmed to one of the high and low states to be an open or short circuit. Even though this method can adjust the GCR of the MOS transistor
221
, the resistor network
223
consumes a lot of chip area and makes the circuit quite complicated. Moreover, it can only adjust the equivalent resistance of the resistor network
223
from some specific values, instead in a continuous range. Therefore, further improvement on the circuit and method for tuning the current level of the reference cell in flash memory is desired.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a trim circuit and method for tuning the current level of a reference cell in a flash memory by means of a voltage divider added to the reference cell to adjust the GCR of the reference cell. Particularly, the voltage divider includes a first and second voltage dividing units, and at least one of the units includes a programmable flash cell to serve as a variable resistor whose resistance is controlled by programming the flash cell to the desired level.
REFERENCES:
patent: 5859796 (1999-01-01), Cleveland
Fan Tso-Hung
Lu Tao-Cheng
Yeh Chih-Chieh
Luu Pho M.
Macronix International Co. Ltd.
Phung Anh
Rabin & Berdo P.C.
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