Trilayer/bilayer solder bumps and fabrication methods therefor

Details Trilayer/bilayer solder bumps and fabrication methods therefor Trilayer/bilayer solder bumps and fabrication methods therefor

2000-05-23

2002-12-10

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S612000, C438S613000, C438S614000, C438S615000, C257S737000, C257S738000, C257S778000, C257S779000, C257S780000, C257S781000

Reexamination Certificate

active

06492197

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to microelectronic devices and fabrication methods therefor, and more particularly to structures and methods of forming electrical and mechanical connections for a microelectronic substrate, and the connections so formed.
BACKGROUND OF THE INVENTION
Solder bump technology is widely used for electrical and mechanical interconnection of microelectronic substrates. For example, an integrated circuit chip may be connected to a circuit board or other next level packaging substrate using solder bumps. This connection technology also is referred to as “Controlled Collapse Chip Connection—C4” or “flip-chip” technology, and will be referred to herein as “solder bumps”.
In solder bump technology, an “UnderBump Metallurgy” (UBM) may be formed on a microelectronic substrate having contact pads thereon, for example by evaporation and/or sputtering. A continuous underbump metallurgy generally is provided on the pads and on the substrate between the pads, in order to allow current flow during subsequent solder plating.
In order to define the sites for solder bump formation over the contact pads, a mask is formed, for example by forming a thick layer of photoresist on the underbump metallurgy and patterning the photoresist to expose the underbump metallurgy over the contact pads. Solder pads then may be formed on the exposed areas of the underbump metallurgy, over the contact pads, by electroplating. The plated solder accumulates in the cavities of the photoresist, over the contact pads. The underbump metallurgy between the plated solder then may be etched, using the solder as an etch mask, to break the electrical connection between the solder bumps. The plated solder then may be reflowed to form solder bumps. During reflow, the solder bump also may alloy with the underbump metallurgy, to form an intermetallic. Solder bump fabrication methods and structures are described in U.S. Pat. No. 5,162,257 to Yung; U.S. Pat. No. 5,293,006 to Yung; U.S. Pat. No. 5,447,264 to Koopman et al.; U.S. Pat. No. 5,767,010 to Mis et al.; U.S. Pat. No. 5,793,116 to Rinne et al.; U.S. Pat. No. 5,892,179 to Rinne et al.; U.S. Pat. No. 5,902,686 to Mis; and U.S. Pat. No. 5,963,793 to Rinne et al., and need not be described further herein.
As microelectronic technology continues to advance, it may become increasingly desirable to use solder bump technology in an increasing variety of microelectronic devices. Conventional solder bumps use alloys of lead (Pb)-tin (Sn) solder. In these solder bumps, it may be desirable to maintain a high lead content to allow a high degree of flexibility in the solder bump, which can thereby absorb mechanical stresses that may be caused by thermal expansion coefficient mismatches between the substrates that are connected by the solder bumps. Unfortunately, as the lead content of lead-tin solder increases above or below 37% from eutectic lead-tin solder (63 Sn-37 Pb), the melting point of the solder bump generally increases. This increased melting point may require higher temperatures for solder reflow and/or joining. These higher temperatures may damage microelectronic devices in a microelectronic substrate. Moreover, it may be more difficult to form a strong connection between the solder bump and the underbump metallurgy as the lead content continues to increase.
Attempts to provide high performance solder bump connections are described in U.S. Pat. No. 4,673,772 to Satoh et al.; U.S. Pat. Nos. 5,130,779 and 5,251,806 to Agarwala et al.; U.S. Pat. No. 5,542,174 to Chiu; U.S. Pat. Nos. 5,553,769, 5,859,470 and 5,920,125 to Ellerson et al.; U.S. Pat. No. 5,470,787 to Greer; and in a publication entitled An Extended Eutectic Solder Bump for FCOB to Greer, 1996 Electronic Components and Technology Conference, pp. 546-551. However, notwithstanding these and other attempts, there continues to be a need for solder bumps and fabrication methods that can maintain a high lead content, can reflow at relatively low temperatures and/or can alloy effectively with an underbump metallurgy.
SUMMARY OF THE INVENTION
The present invention can provide trilayer/bilayer solder bump fabrication methods by plating a first solder layer on an underbump metallurgy, plating a second solder layer having higher melting point than the first solder layer on the first solder layer and plating a third solder layer having lower melting point than the second solder layer on the second solder layer. The structure then is heated to below the melting point of the second solder layer but above the melting point of the first solder layer and the third solder layer, to alloy at least some of the first solder layer with at least some of the underbump metallurgy and to round the third solder layer. Accordingly, a trilayer solder bump may be fabricated wherein the first and third solder layers melt at lower temperatures than the second solder layer, to thereby round the outer surface of the solder bump and to alloy the base of the solder bump to the underbump metallurgy, while allowing the structure of the intermediate layer to be preserved.
Solder bump fabrication as described above may be particularly useful with lead-tin solder wherein the first solder layer comprises eutectic lead-tin solder, the second solder layer comprises lead-tin solder having higher lead content than eutectic lead-tin solder and the third solder layer comprises eutectic lead-tin solder. In these embodiments, the first and third eutectic lead-tin solder layers can provide a lowest melting point for rounding the top and alloying the base of the solder bump. However, the high lead content of the intermediate (second) solder layer may be preserved to provide flexibility for the bump. Moreover, since the first, second and third solder layers are plated, the columnar plated structure within the intermediate solder layer may be preserved, to thereby allow further increases in flexibility. Thus, the second solder layer may be maintained in its “as plated” condition.
Embodiments of the invention may be used with underbump metallurgy systems that include an outer layer of copper. In these embodiments, heating may be performed to alloy sufficient tin from the first solder layer with at least some of the outer layer comprising copper, such that the first solder layer is converted to a fourth solder layer having the same lead content as the second solder layer. This can create a bilayer solder bump wherein the second and fourth solder layers have the same lead content, after reflow, and a eutectic third (outer) rounded layer caps the second solder layer. In yet other embodiments, heating is performed to alloy at least some tin from the first solder layer with at least some of the copper outer layer of the underbump metallurgy, such that the first solder layer is converted to a fourth solder layer having higher lead content than eutectic lead-tin solder, but not having the same lead content as the second solder layer. Accordingly, these embodiments may provide trilayer reflowed solder bumps.
In yet other embodiments, the thickness and/or composition of the copper outer layer and/or of the first solder layer may be selected so that upon heating, sufficient tin from the first solder layer is alloyed with all of the copper in the outer underbump metallurgy layer, such that the first solder layer is converted to a fourth solder layer having same lead content as the second solder layer. Bilayer solder bumps thereby may be provided. In yet other embodiments, the thickness and/or composition of the first solder layer and/or of the outer layer of the underbump metallurgy maybe selected to alloy some tin from the first solder layer with all of the copper in the outer layer, such that all of the outer layer is converted to copper-tin alloy and the first solder layer is converted to a fourth solder layer having higher lead content than eutectic lead-tin solder, but not the same lead content as the second solder layer.
Other embodiments of the present invention may be used with underbump metallurgy systems having a nickel outer lay

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