Triggered DDS pulse generator architecture

Details Triggered DDS pulse generator architecture Triggered DDS pulse generator architecture

2007-10-09

2007-10-09

Ngo, Chuong D (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S272000

Reexamination Certificate

active

10739761

ABSTRACT:
A triggered DDS generator architecture accumulates a phase increment value in response to a DDS clock to generate phase accumulator values for addressing a waveform lookup table which contains a desired output signal. A time measurement circuit determines a time interval between the arrival of a trigger signal and a subsequent cycle of the DDS clock, which time interval is used to either adjust an initial phase accumulator value or delay the DDS clock so that a constant time is maintained between the arrival of the trigger signal and the desired output signal.

REFERENCES:
patent: 5598440 (1997-01-01), Domagala
patent: 7084676 (2006-08-01), Harron et al.
patent: 7124153 (2006-10-01), Grushin

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