Trigger signal generating circuit with extraneous pulse preventi

Details Trigger signal generating circuit with extraneous pulse preventi Trigger signal generating circuit with extraneous pulse preventi

1993-03-29

1995-01-10

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Applications

Measuring or testing

377 28, 377 55, 327291, H03K 2140

Patent

active

053814517

ABSTRACT:
A signal generating circuit includes a counter for counting up input clock pulses to output a trigger signal when counting up to a predetermined number of pulses, a CPU for outputting a mask request of a first trigger signal, a first flip-flop for storing the mask request of the CPU, a second flip-flop for latching a normal output signal of the first flip-flop by the trigger signal of the counter, and an AND circuit for calculating a logical sum of a mask request signal output from the second flip-flop and the trigger signal output from the counter. Thus, the trigger signal generating circuit masks the first trigger signal output from the counter and prevents the output of a superfluous trigger signal when a timing of a trigger signal generation is delayed.

REFERENCES:
patent: 3801917 (1974-04-01), Weinstein
patent: 4392733 (1983-07-01), Beppu et al.
patent: 4968907 (1990-11-01), Pepper
patent: 4979194 (1990-12-01), Kawano

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