Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Bidirectional rectifier with control electrode
Reexamination Certificate
2001-02-12
2003-04-01
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Bidirectional rectifier with control electrode
C257S122000, C257S124000, C257S133000, C257S140000, C257S141000, C257S146000, C257S162000, C257S355000, C257S360000, C257S361000, C257S362000
Reexamination Certificate
active
06541801
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a triode ac switch (triac) and, more particularly, to a triac with a holding voltage that is greater than the dc bias voltages that are on the to-be-protected nodes.
2. Description of the Related Art
A triode ac switch (triac) is a device that provides an open circuit between a first node and a second node when the first-to-second node voltage is positive and less than a trigger voltage. When the first-to-second node voltage rises to be equal to or greater than the trigger voltage, the triac provides a low-resistance current path between the first and second nodes. Further, once the low-resistance current path has been provided, the triac maintains the current path as long as the first-to-second node voltage is positive and equal to or greater than a holding voltage that is lower than the trigger voltage.
The triac, which is a symmetrical device, also provides an open circuit between the second node and the first node when the second-to-first node voltage is positive and less than the trigger voltage. When the second-to-first node voltage rises to be equal to or greater than the trigger voltage, the triac provides a low-resistance current path between the second and first nodes. Further, once the low-resistance current path has been provided, the triac maintains the current path as long as the second-to-first node voltage is positive and equal to or greater than the holding voltage. Thus, the triac provides an identical structure to both the first and second nodes.
As a result of these characteristics, triacs have been used to provide electrostatic discharge (ESD) protection for semiconductor circuits. When used for ESD protection, the first node becomes a first to-be-protected node, and the second node becomes a second to-be-protected node.
The triac operates within an ESD protection window that has a maximum voltage defined by the destructive breakdown level of the to-be-protected nodes, and a minimum voltage (also known as a latch-up voltage) defined by any dc bias that is on the to-be-protected nodes. The trigger voltage of the triac is set to a value that is less than the maximum voltage of the window, while the holding voltage is set to a value that is greater than the minimum voltage of the window.
Thus, when the voltage across the first to-be-protected node and the second to-be-protected node is positive and less than the trigger voltage, the triac provides an open circuit between the first to-be-protected node and the second to-be-protected node. Similarly, when the voltage across the second to-be-protected node and the first to-be-protected node is positive and less than the trigger voltage, the triac also provides an open circuit between the second to-be-protected node and the first to-be-protected node.
However, when the first to-be-protected node receives a voltage spike that equals or exceeds the trigger voltage, such as when an ungrounded human-body contact occurs, the triac provides a low-resistance current path from the first to-be-protected node to the second to-be-protected node. Similarly, when the second to-be-protected node receives a voltage spike that equals or exceeds the trigger voltage, the triac provides a low-resistance current path from the second to-be-protected node to the first to-be-protected node.
In addition, once the ESD event has passed and the voltage on the first to-be-protected node falls below the holding voltage, the triac again provides an open circuit between the first to-be-protected node and the output node. Similarly, after the ESD event has passed and the voltage on the second to-be-protected node falls below the holding voltage, the triac again provides an open circuit between the second to-be-protected node and the first to-be-protected node.
FIG. 1
shows a cross-sectional diagram that illustrates a conventional triac
100
. As shown in
FIG. 1
, triac
100
has spaced apart n-wells
112
and
114
which are formed in a p-type material
110
, such as a well or a substrate. In addition, triac
100
has a n+ region
116
and a p+ region
118
which are formed in n-well
112
, and a n+ region
120
which is formed in p-type material
110
and n-well
112
. N+ and p+ regions
116
and
118
, in turn, are both connected to a first to-be-protected node
122
.
As further shown in
FIG. 1
, triac
100
also has a n+ region
124
and a p+ region
126
which are formed in n-well
114
, and a n+ region
128
which is formed in p-type material
110
and n-well
114
. N+ and p+ regions
124
and
126
, in turn, are both connected to a second to-be-protected node
130
.
Triac
100
further has a channel region
132
that is defined between n+ region
120
and n+ region
128
. In addition, triac
100
has a gate oxide layer
134
that is formed on material
110
over channel region
132
, and a gate
136
that is formed on gate oxide layer
134
. N+ (drain and source) regions
120
and
128
, gate oxide layer
134
, and gate
136
define a NMOS transistor
140
which is typically formed to be identical to the to-be-protected MOS transistors in the circuit.
In operation, when the voltage on the drain of a conventional NMOS transistor spikes up, the drain-to-substrate junction of the NMOS transistor breaks down, for example, at 7 volts, while the gate oxide layer that isolates the gate from the drain destructively breaks down at, for example, 10-15 volts.
When a voltage across nodes
122
and
130
is positive and less than a trigger voltage, the voltage reverse biases the junction between n+ (drain) region
120
-well
112
and p-type material
110
, and forward-biases the junction between n+ (source) region
128
-well
114
and p-type material
110
. The reverse-biased junction, in turn, blocks current from flowing from node
122
to node
130
.
On the other hand, when the voltage across nodes
122
and
130
is equal to or greater than the trigger voltage, the reverse-biased junction breaks down due to avalanche multiplication. Since NMOS transistor
140
is formed to be identical to the to-be-protected MOS transistors, the junction between n+ region
120
and p-type material
110
breaks down at the same time that the to-be-protected MOS transistors experience junction break down.
Since junction break down occurs before the MOS transistors experience destructive gate oxide break down, triac
100
turns on before destructive gate oxide breakdown occurs, thereby protecting the MOS transistors. Thus, the junction break down voltage, which is less than the voltage level that causes destructive gate oxide break down, functions as the trigger voltage.
The breakdown of the junction due to avalanche multiplication causes a large number of holes to be injected into p-type material
110
, and a large number of electrons to be injected into n-well
112
. The holes injected into material
110
turn on a npn transistor that utilizes n+ region
128
as an emitter, p-type material
110
as a base, and n-well
112
as a collector.
When the npn transistor turns on, n+ (emitter) region
128
injects electrons into (base) material
110
. Most of the injected electrons diffuse through (base) material
110
and are swept from (base) material
110
into (collector) n-well
112
by the electric field that extends across the reverse-biased junction. The electrons in (collector) n-well
112
are then collected by n+ region
116
.
A small number of the electrons injected into (base) material
110
recombine with holes in (base) material
110
and are lost. The holes lost to recombination with the injected electrons are replaced by holes injected into (base) material
110
by the broken-down reverse-biased junction and, as described below, by the collector current of a pnp transistor.
The electrons that are injected and swept into n-well
112
also decrease the potential of n-well
112
in the region that lies adjacent to p+ region
118
, and eventually forward bias the junctio
Hopper Peter J.
Vashchenko Vladislav
Loke Steven
National Semiconductor Corporation
Pickering Mark C.
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