Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2000-10-11
2003-02-04
Nelms, David (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S230080
Reexamination Certificate
active
06515885
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuits, and more specifically to an address input circuit for semiconductor memory devices.
BACKGROUND OF THE INVENTION
Integrated circuits, such as microprocessors and memories, routinely transmit data to one another. However, an integrated circuit receiving data may not be able to process the data immediately upon receipt because the integrated circuit is in the midst of other operations. For example, a memory may not be able to access data from some memory cells whose addresses are transmitted from a microprocessor because the memory is performing other internal operations. Therefore, buffers are necessary at the inputs of many integrated circuits, such as memories. Data, such as a memory address, is stored in the buffer until the integrated circuit is ready to process the data.
Because the integrated circuit may require the received data immediately, the buffer should be fast. Conventional buffers include circuitry, such as multiplexors and permanent feedback loops, to latch the address.
FIG. 1
illustrates a prior art buffer
100
, including successively coupled input, gain, and output stages
102
,
104
,
114
. The prior art buffer includes a multiplexor
110
and an inverter latch
112
in its output stage
114
. An address signal, A
IN
, is sampled and inverted by the input stage
102
when a relatively low voltage is applied at EN* (or address enable signal complement). When ADDR TRAP (or address trap signal) is biased with a relatively low voltage, the multiplexor
110
couples the sampled address signal into the output stage
114
where the sampled address signal is latched at the inverter latch
112
, and further inverted to provide A
OUT
(or latched address signal).
At least five gate delays are encountered in this buffer, greatly diminishing the speed of the buffer. Buffer speed is also reduced by the permanent feedback loop formed by the inverter latch
112
which requires relatively more time to change its state.
There is a need to increase buffer speed. Thus, there is a further need to reduce the circuitry in the path that the sampled address signal must travel in the buffer while maintaining the ability to reliably buffer addresses.
SUMMARY OF THE INVENTION
An address buffer for a memory device comprises an input inverter and a pair of inverters having a multiplexed feedback loop operating as a multiplexed address output latch. An output of the latch is inverted again to provide the address to the memory device. Providing the multiplexor in a feedback loop reduces gate delays encountered in prior input buffers.
In one embodiment, the address input buffer uses address enable signals for controlling both a tri-state input stage, and for enabling the feedback loop in the address output latch. Using the same set of address enable signals for both the input stage and the feedback loop of the address output latch, simplifies control of the address buffer.
When the input stage samples the address, the feedback loop is inoperative. When the input stage is not enabled, the feedback loop latches the address. Furthermore, the feedback loop is not permanent, only being activated when the tri-state input stage is disabled. Because the feedback loop is not permanent and the multiplexor is not in the speed path that the sampled address signal must travel, the speed of the buffer circuit is enhanced over prior devices having either a multiplexor in the speed path or a series of logic gates to perform latching functions. Furthermore, the number of gates required to implement the address buffer is reduced.
In one embodiment, the tri-state input stage is operatively coupled to the address output latch. The tri-state input stage includes series coupled pairs of N and P channel transistors. The address signal is provided to gates of one P channel and one N channel transistor which form an inverter. The other two transistors have their gates coupled to the address enable signal and its complement for enabling the inverter. An output of the inverter is coupled to the address output latch which comprises two series coupled inverters. An output of the second inverter of the latch is fed back through a multiplexor to an input of the first inverter of the latch. The address enable signal and its complement provide control signals to the multiplexor. The output of the address output latch is coupled to a third inverter.
In another embodiment, the multiplexor comprises an N channel transistor operatively coupled to the complement of the address enable signal. A P channel transistor is operatively coupled to the address enable signal and in parallel with the N channel transistor.
A method of operating the buffer comprises sampling a signal. The sampled signal is inverted. The inverted sampled signal is latched. Finally, the latched signal is inverted. The sampling and latching steps occur mutually exclusively. Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.
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Auduong Gene N.
Nelms David
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