Tri-state type driver circuit

Details Tri-state type driver circuit Tri-state type driver circuit

1983-05-03

1985-09-10

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307247R, 307585, 307270, H03K 19094, H03K 17284, H03K 1920, H03K 3037

Patent

active

045409048

ABSTRACT:
An FET complementary pair provides the output to a data line. A data input line is coupled to the gate of the P-FET via an OR gate configuration, and to the gate of the N-FET via an AND gate configuration. The output of each gate configuration is cross-connected to an input of the other. When the input data state changes, the two gate configurations provide delays which are effectively in tandem, so that the FET which was ON is first turned OFF, and after a short delay the other is turned ON. This delay ensures that both FET's are not ON at the same time, which prevents an undesirable power flow. To provide a high impedance "float" state, an enable input and its complement are connected to the AND and OR gate configurations respectively.

REFERENCES:
patent: 3906255 (1975-09-01), Mensch, Jr.
patent: 4280065 (1981-07-01), Minato et al.
patent: 4350906 (1982-09-01), Gillberg
patent: 4363978 (1982-12-01), Heimbigner
patent: 4465945 (1984-08-01), Yin
Askin et al., "Off-Chip Driver", IBM TDB, vol. 21, No. 3, pp. 1044-1048, 8/1978.
Griffin et al., "High Speed Complementary Driver Circuit", IBM TDB, vol. 24, No. 5, pp. 2558-2559, 10/1981.

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