Tri-state output circuit utilizing a BiCMOS inverter circuit

Details Tri-state output circuit utilizing a BiCMOS inverter circuit Tri-state output circuit utilizing a BiCMOS inverter circuit

1991-04-22

1992-07-21

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307473, 307475, 307570, H03K 1902, H03K 19094

Patent

active

051325683

ABSTRACT:
A tri-state logic circuit of a BiCMOS having a power saving characteristic, a strong noise durability, a desirable driving characteristic and switching charaacteristic is disclosed. The circuit comprises PMOS transistors M1,M5 and NMOS transistors M2,M3,M4,M6,M7,M8,M9 and bipolar transistors Q1,Q2 and a capacitor C1.

REFERENCES:
patent: 4769561 (1988-09-01), Iwamura et al.
patent: 4779014 (1988-10-01), Masuoka et al.
patent: 4806797 (1989-02-01), Yamazaki
patent: 4985645 (1991-01-01), Tsutui

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