Tri-state logic gate having reduced Miller capacitance

Details Tri-state logic gate having reduced Miller capacitance Tri-state logic gate having reduced Miller capacitance

1983-12-29

1986-04-29

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307300, 307443, H03K 19003, H03K 19088, H03K 19092, H03K 1760

Patent

active

045859590

ABSTRACT:
A three state gate having an output capable of assuming an active high, an active low, or a high impedance state is disclosed that has circuitry for removing the inherent Miller capacitive charge from an output transistor during the high impedance state. An output means includes an upper transistor for supplying current to the output and a lower transistor for sinking current from the output. A phase-splitter means coupled to the output means determines the conductivity of the upper and lower transistors. The phase-splitter means is responsive to an input signal and an output enable signal. A first transistor has a collector coupled to the base of the upper output transistor. A second transistor has a collector coupled to the base of the lower output transistor, and a base coupled to the emitter of the first transistor. A third transistor has a collector coupled to the base of the first transistor. A fourth transistor has an emitter coupled to an emitter of the third transistor and the output enable terminal. A fifth transistor has a base coupled to a collector of the fourth transistor, a collector coupled to a base of the phase-splitter transistor, and an emitter coupled to the base of the lower output transistor.

REFERENCES:
patent: 3641362 (1972-02-01), Gamble
patent: 3980898 (1976-09-01), Priel
patent: 4311927 (1982-01-01), Ferris
patent: 4330723 (1982-05-01), Griffith
patent: 4339675 (1982-07-01), Ramsey
patent: 4339676 (1982-07-01), Ramsey
patent: 4430585 (1984-02-01), Kirk, Jr.
patent: 4449063 (1984-05-01), Ohmichi et al.
patent: 4454432 (1984-06-01), Wood

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