Tri-state CMOS driver having reduced gate delay

Details Tri-state CMOS driver having reduced gate delay Tri-state CMOS driver having reduced gate delay

1982-09-03

1984-08-14

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307270, 307451, H03K 19017, H03K 19094, H03K 1920

Patent

active

044659458

ABSTRACT:
A Tri-State circuit element is constructed which is uniquely suited for use in large scale integrated circuit devices wherein a relatively large number of such Tri-State circuits are utilized to drive other circuitry contained within the integrated circuit device. One embodiment of a Tri-State circuit is constructed utilizing a single NAND gate (73), a single inverter (74), a single P channel transistor (76), and two N channel transistors (77, 78) yielding a circuit having a propagation delay of only two gate delays and requiring a total of only nine transistors. Another embodiment of this invention is a Tri-State circuit constructed utilizing a single NOR gate (84), a single inverter (83), a single N channel transistor (88), and two P channel transistors (86, 87). In this embodiment of my invention, a total of nine MOS transistors are required, and the propagation delay between the input terminal and the output terminal is equal to two gate delays.

REFERENCES:
patent: 3896430 (1975-07-01), Hatsukano
patent: 3928773 (1975-12-01), Oguey et al.
patent: 4037114 (1977-07-01), Stewart et al.
patent: 4121203 (1978-10-01), Edwards et al.
patent: 4345172 (1982-08-01), Kobayashi et al.
Kraft et al., "Tristate Driver Utilizing Bipolar-Complementary Metal-Oxide Semiconductor Technology", IBM Tech. Disc. Bull., vol. 16, No. 8,1-'74, pp. 2677-2678.

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