Tri-state bus controller

Details Tri-state bus controller Tri-state bus controller

1998-10-09

2000-09-19

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

327293, H03K 384

Patent

active

061218146

ABSTRACT:
A bus master controller comprising a plurality of logic modules, each module coupled to a separate bus driver circuit. The logic module operates using a "break-before-make" protocol derived from a finite state machine, delay element and exclusive-OR gate. The finite state machine generates a predetermined sequence that requires an "assert" signal to always be delayed with respect to a "de-assert" signal, thus eliminating the possibility that more than one set of bus drivers will be coupled to the bus at any one time.

REFERENCES:
patent: 4347617 (1982-08-01), Murano et al.
patent: 4348597 (1982-09-01), Weber
patent: 5172397 (1992-12-01), Llewellyn

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