Tri state buffer circuit for dual power system

Details Tri state buffer circuit for dual power system Tri state buffer circuit for dual power system

1992-02-19

1993-11-30

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307473, 3072962, 307443, H03K 190175, H03K 1900

Patent

active

052668495

ABSTRACT:
A CMOS tri-state buffer circuit transfers digital signals between a first digital circuit system operating at 3.3 Volts and a second system operating at 5 Volts. The buffer circuit receives an active high enable signal and a data signal as inputs to a tri-state select network. When the enable signal is high, data is propagated through a driver stage and onto a data bus in the second system. Driver clamp circuitry and an n-well voltage controller operate conjunction with the driver stage to prevent the 5 volt supply of the second system from interfering with the circuitry of the of the 3.3 Volt system. A clamped line driver transmits signals from the 5 Volt system to the 3.3 Volt system.

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patent: 5017811 (1991-05-01), Worley
patent: 5084637 (1992-01-01), Gregor
patent: 5144165 (1992-09-01), Dhong et al.
patent: 5153457 (1992-10-01), Martin et al.
patent: 5159216 (1992-10-01), Taylor et al.

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