Tri-mode clock generator to control memory array access

Details Tri-mode clock generator to control memory array access Tri-mode clock generator to control memory array access

2007-05-29

2007-05-29

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S193000

Reexamination Certificate

active

10948554

ABSTRACT:
A clock generator is provided that is compatible with both DDR1and DDR2applications. The internal YCLK signal is turned on only when an active read or write occurs on the integrated circuit memory, even though the main chip clock is always running. A circuit block within the clock generator detects when a read or write is active and initiates a YCLK signal on the next falling edge of the internal clock. Two separate mechanisms are used for determining when to terminate the YCLK. One mechanism is a timer path and the other is a path determined by DDR1and DDR2control signals. The timer path is strictly time based and is the same for DDR1and DDR2parts or modes of operation. The other signal path is different for DDR1and DDR2operating modes. A DDR1control signal turns off YCLK at the next rising edge of the internal clock, and a DDR2control signal turns off YCLK at the next falling edge of the internal clock.

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