Tri-level input buffer

Details Tri-level input buffer Tri-level input buffer

1981-10-02

1984-05-15

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307452, H03K 19096, H03K 1920

Patent

active

044490658

ABSTRACT:
A simple six-transistor input buffer for generating and applying binary function test signals to associated circuitry in an integrated circuit package. The buffer recognizes three different voltage levels of an input signal that is applied to a single input test pin and generates three corresponding binary output signals that may be used for testing various functions of the associated circuitry.

REFERENCES:
patent: 3609411 (1971-09-01), Ma et al.
patent: 3950656 (1976-04-01), Sumida et al.
patent: 3969633 (1976-07-01), Paluck et al.
patent: 4100429 (1978-07-01), Adachi
patent: 4163907 (1979-08-01), Schroeder et al.
patent: 4302690 (1981-11-01), Gollinger et al.
patent: 4363978 (1982-12-01), Heimbigner
Scarpero, Jr. "Field-Effect Transistor Bidirectional Driver Control Circuit", IBM Tech. Discl. Bull., vol. 16, No. 8, pp. 2442-2443, 1/74.
Griffin et al., "High Speed Complementary Driver Circuit", IBM Tech. Discl. Bull., vol. 24, No. 5, pp. 2558-2559; 10/1981.
Moraga, "A Ternary One-Trit Multiplier"; Digital Processes (Pub.) 2, No. 3 (Autumn) 1976, pp. 241-243.

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