Tri-level dynamic element matcher allowing reduced reference...

Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C341S172000

Reexamination Certificate

active

07812753

ABSTRACT:
Systems and methods using the same to achieve a tri-level multi-bit delta-sigma DAC having reduced power consumption and voltage droop have been achieved. A new rotation-based first order noise-shaping Dynamic Element Matcher (DEM) technique for use with 3-level unit elements have been disclosed. Reduced reference loading has been achieved when the tri-level DEM scheme is applied to switched capacitor implementations in particular. Furthermore a differential switched-capacitor DAC implementation, which enables use of the DEM technique is disclosed. The invention allows reduced circuit complexity required to implement a N-bit DAC when constructed using 3-level unit elements.

REFERENCES:
patent: 5134402 (1992-07-01), Miyoshi
patent: 5274375 (1993-12-01), Thompson
patent: 6573850 (2003-06-01), Pennock
patent: 6952176 (2005-10-01), Frith et al.
patent: 7079063 (2006-07-01), Nguyen et al.
patent: 7388533 (2008-06-01), Kim et al.
patent: 7511650 (2009-03-01), Chang et al.
patent: 7538705 (2009-05-01), Deval et al.
patent: 2005/0156773 (2005-07-01), Galton
patent: 2007/0069934 (2007-03-01), Mills et al.
patent: 2008/0309536 (2008-12-01), Le Guillou et al.
patent: 2009/0016544 (2009-01-01), Li et al.
patent: 2010/0103014 (2010-04-01), Quiquempoix et al.
“A 108 dB SNR, 1.1 mW Oversampling Audio DAC With A Three-level DEM Technique,” by Nguyen et al., IEEE Journal of Solid-State Circuits, vol. 43, No. 12, Dec. 2008, pp. 2592-2600.
“A 108cB SNR 1.1mW Oversamplinc Audio DAC with a Three-Level DEM Technique,” by Nguyen et al., 2008 IEEE Iinternational Solid-State Circuits Conference, ISSCC 2008 / Session 27 / Delta-Sigma Data Converters / 27.1, pp. 488-489 & 630.
“TP 11.5: A Digitally-Corrected 20b Delta-Sigma Modulator,” by Thompson et al., 1994 IEEE International Solid-State Circuits Conference, ISSCC94 / Session 11 / Oversampled Data Conversion / Paper TP 11.5, pp. 194-195.
“Linearity Enhancement of Multibit Delta-Sigma A/D and D/A Converters Using Data Weighted Averaging,” by Baird et al., IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 42, No. 12, Dec. 1995, pp. 753-762.
“Techniques for Preventing Tonal Behavior of Data Weighted Averaging Algorithm in Sigma-Delta Modulators,” by Morteza Vadipour, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 47, No. 11, Nov. 2000, pp. 1137-1144.
IEEE Press/John Wiley & Sons Inc., 1997, ISBN 0-7803-1045-4, “Understanding Delta Sigma Data Converters,” by R. Schreier et al., Chapter 6, Sections 6.3 and 6.4, pp. 184-198, 218, & 278-281.
IEEE Pess, 2005, ISBN 0-471-46585-2, “Delta-Sigma Data Converters: Theory, Design and Simulation,” by S. R. Norsworthy et al., Chapter 8, Section 3, pp. 247-264.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Tri-level dynamic element matcher allowing reduced reference... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Tri-level dynamic element matcher allowing reduced reference..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Tri-level dynamic element matcher allowing reduced reference... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4223004

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.