Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to conductive state
Reexamination Certificate
1998-05-27
2001-05-08
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to conductive state
C438S132000, C438S251000
Reexamination Certificate
active
06228689
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87105972, filed Apr. 18, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a trench style bump and its fabrication method, and more particular, to an application of employing the trench style bump into flip chip technique, such as chip on glass (COG) and ball grid array (BGA).
2. Description of the Related Art
Integration circuits (ICs) have reached every part of our daily lives. However, the process of fabricating an IC is very complex. Hundreds of steps are needed for making an IC. The fabrication normally takes one or two month to complete. The IC industry is a high technology industry including four main branches: IC design, wafer fabrication, wafer testing, and wafer packaging. Thus, IC industry is not only an advanced technology industry, but also a high risky industry which needs a tremendous capital to maintain.
In a conventional package of an IC chip, a lead frame is used to electrically connect a semiconductor and an external wire of the package. However, as the integrated circuit grows more and more delicate and complex, the required wire increases greatly in the same package volume. The traditional lead frame technique can not meet the requirement at all. Therefore, to develop a new package which contains and connects more conducting wires are required.
One of the package technique which accommodates a large number of wires is BGA package. A BGA package is normally in a square shape in which the conducting terminal is in a form a solder ball. This terminal is designed and installed on a bonding pad of a printed wire board (PWB), a printed circuit board (PCB), or some other devices to connected.
In practice, a conventional BGA is a miniature of a multi-layered PCB, which comprises an IC chip, to electrically connect each other via various ways. The connections between conductors are achieved by via or plug.
Another design which accommodates and connect a large number of wires in a limited region is glass on chip (COG). The wiring or circuit is built in a glass substrate. Through some conducting device or terminal on the chip, for example, gold bump, the chip is coupled directly to the circuit in the glass substrate.
FIG. 1
a
to
FIG. 1
f
show a conventional method of fabricating a gold bump. Referring to
FIG. 1
a
, an aluminum (Al) pad
102
and a passivation layer
104
are formed on a silicon chip
100
. A wafer cleaning step is performed on the silicon chip
100
.
In
FIG. 1
b
, an under bump material (UMB)
106
which comprises a titanium tungsten layer (TiW)
106
A and a gold layer
106
B is formed over the silicon chip
100
.
In
FIG. 1
c
, using a photo-mask, a photo-resist layer
108
with an opening
110
aligned with the Al pad
102
therein is formed over the UBM
106
. In
FIG. 1
d
, a gold layer
110
A is formed to fill the opening
110
.
In
FIG. 1
e
, the photo-resist layer
108
is removed, and then the UBM
106
is removed to complete the formation of a gold bump
106
B shown as
FIG. 1
f.
FIG. 2
a
to
FIG. 2
b
show a conventional method of employing the above metioned gold bump structure a flip chip technique. In
FIG. 2
a
, a substrate
200
, for example, a glass substrate or a printed circuit board is provided. A cleaning process is performed on the substrate
200
first. On the substrate
200
, an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACA)
202
is formed. In the figure, the particles contained by the ACF/ACA
202
represent the conductive particles.
In
FIG. 2
b
, a silicon chip
100
having a gold bump
110
B as described above is laminated on the substrate
200
. It is known that the substrate
200
normally includes an organic material. In the case of printed circuit board, bismalemide triazine (BT) compound is used to form a printed circuit board. This kind of material is easily bent and deformed due to thermal expansion, moisture, or inappropriate handle. As shown in the figure, the deformation causes a bad contact between the gold bump and the substrate. Consequently, an open circuit is very likely to happen. In addition, if the surface level of the gold bump
100
is formed non-uniformly, the open circuit is even more obvious.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a trench style metal bump of a chip and a method of fabricating the same. The formation of a trench in the metal bump causes the conductive particles in the ACF/ACA to be trapped therewithin. Therefore, the bad contact caused by the bent substrate or uneven surface of the bump is improved.
It is therefore another object of the invention to provide a method of laminating a silicon chip having a trench style bump with the substrate with a good contact. An ultra sonic vibration is performed to the substrate laterally during lamination, so that the conductive particles in the ACF/ACA are trapped within the trench more effectively. As a consequence, the bad contact between the bump and the substrate is further improved.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method of fabricating a trench style bump. A silicon chip which comprises a metal pad, a passivation layer on a part of the silicon chip which is not covered by the metal pad, and a under bump material over the silicon chip, is provided. A first photo-resist layer is formed and patterned, so that a first opening aligned with the metal pad is formed, and the under bump material is exposed within the first opening. A first bump material layer is formed to fill the first opening. A second photo-resist layer is formed and patterned, so that at least a second opening is formed on the first bump material layer, and the under bump material is exposed within the second opening. A second bump material layer is formed to fill the second opening. The first and the second photo-resist layers are removed, so that the first bump material layer and the second bump material layer are combined as one trench style bump. A part of the under bump material is removed with the trench style bump as a mask.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a trench style bump, which is formed on a silicon chip comprising a metal pad and a passivation layer. The trench style bump comprises an under bump layer formed on the metal pad, and a bump having at least a trench on a surface thereof.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a flip chip technique which employs a silicon chip having a trench style bump. A substrate on which an anisotropic conductive film/anisotropic conductive paste is formed is provided. The silicon chip is laminated on the substrate, so that the trench style bump is contacted with the substrate. The substrate laterally is vibrated using an ultra sonic wave, and a pressing force is applied on the silicon chip towards the substrate during vibration.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 4187868 (1980-02-01), Rudolphi
patent: 4478364 (1984-10-01), Ditzig
patent: 4992847 (1991-02-01), Tuckerman et al.
patent: 5672548 (1997-09-01), Culane et al.
patent: 5785799 (1998-07-01), Culane et al.
patent: 5795619 (1998-08-01), Lin et al.
patent: 5847929 (1998-12-01), Berneir
patent: 5900738 (1999-05-01), Khandros et al.
patent: 5906312 (1999-05-01), Zakel et al.
Bowers Charles
Schillinger Laura
Thomas Kayden Horstemeyer & Risley
United Microelectronics Corp.
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