Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1996-09-25
1999-01-26
Fourson, George
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438692, 438699, 438725, H01L 2176
Patent
active
058638288
ABSTRACT:
Disclosed are methods for planarizing a pattern of trenches and pillars on a substrate. The trenches are filled by depositing a filler material to a thickness greater than or equal to their depth. Photoresist is then patterned to open at least some areas overlying at least some of the pillars. Exposed resist and filler are then etched isotropically simultaneously to substantially planarize the pattern. In one embodiment, the ratio of resist etch rate to filler etch rate is greater than 1.0. In another embodiment, planarization may be achieved by etching filler material in nonactive areas without exposing caps of capped pillars, e.g., etching with endpoint detection. Then, caps of the capped pillars may then be exposed. These methods may be used in conjunction with chemical mechanical polishing steps with reduced pattern sensitivity, avoiding dishing and isolated pillar erosion.
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Fourson George
National Semiconductor Corporation
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