Trench isolation without grooving

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including high voltage or high power devices isolated from...

Reexamination Certificate

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Details

C257S506000, C257S510000, C257S513000, C438S221000, C438S296000, C438S426000, C438S435000

Reexamination Certificate

active

06924542

ABSTRACT:
A method and structure to form shallow trench isolation regions without trench oxide grooving is provided. In particular, a method includes a two-step oxide process in which an oxide liner lines the inside surface of a trench and the trench is filled with a bulk oxide layer, preferably using a high density plasma chemical vapor deposition (HDP-CVD) process. The oxide liner and the bulk oxide layer are formed to have similar etch rates. Thus, when etching the oxide liner and the bulk oxide layer between stack structures, a common dielectric top surface is formed that is substantially planar and without grooves.

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patent: 2002/0135025 (2002-09-01), Park

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