Trench isolation structure partially bound between a pair of low

Details Trench isolation structure partially bound between a pair of low Trench isolation structure partially bound between a pair of low

1997-12-19

1999-03-16

Niebling, John F.

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438296, H01L 21326, H01L 2176

Patent

active

058829830

ABSTRACT:
A process is provided for forming to dielectric structures having a relatively low dielectric constant arranged adjacent to the opposed lateral edges of a trench isolation structure. In an embodiment, an opening is etched vertically through a masking layer arranged upon a semiconductor substrate, thereby exposing the surface of the substrate. A patterned photoresist layer is formed upon the masking layer using optical lithography to define the region to be etched. Sidewall spacers made of a low K dielectric material are formed upon the opposed sidewall surfaces of the masking layer within the opening. The sidewall spacers are formed by CVD depositing a dielectric material within the opening and anisotropically etching the dielectric material until only a pre-defined thickness of the material remains upon the masking layer sidewall surfaces. Thereafter, a trench defined between the exposed lateral edges of the sidewall spacers is formed within the substrate. The sidewall spacers permit the lateral width of the spacers to be reduced below the minimum lateral dimension definable using lithography. A trench dielectric is formed within the trench such that the upper portion of the dielectric is bound by the sidewall spacers on opposite ends. The resulting trench isolation structure is less likely to experience current leakage when operating an ensuing integrated circuit which employs the isolation structure.

REFERENCES:
patent: 5130268 (1992-07-01), Liou et al.
patent: 5795811 (1998-08-01), Kim et al.
patent: 5804491 (1998-09-01), Ahn
Wolf, S. and Tauber, R.N., Silicon Processing for the VLSI Era, vol 1, Lattice Press, pp. 198-199, 1986.

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