Trench isolation structure for a semiconductor device with...

Details Trench isolation structure for a semiconductor device with... Trench isolation structure for a semiconductor device with...

2008-04-15

2008-04-15

Wilczewski, Mary (Department: 2822)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S437000

Reexamination Certificate

active

07358150

ABSTRACT:
By forming a non-oxidizable liner in isolation trenches, the creation of compressive stress may be significantly reduced, wherein, in illustrative embodiments, silicon nitride may be used as liner material. For this purpose, the etch behavior of the silicon nitride may be efficiently modified on the basis of an appropriate surface treatment, thereby providing a high degree of material integrity during a subsequent etch process for removing non-modified portions of silicon nitride, which may also be used as an efficient CMP stop layer.

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patent: 6251746 (2001-06-01), Hong et al.
patent: 6657276 (2003-12-01), Karlsson et al.
patent: 7078314 (2006-07-01), Kim et al.
patent: 2004/0198019 (2004-10-01), Yasui et al.
patent: 2004/0212035 (2004-10-01), Yeo et al.
patent: 2005/0116312 (2005-06-01), Lim et al.
patent: 2007/0155121 (2007-07-01), Frohberg et al.

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