Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Patent
1998-04-09
1999-08-31
Crane, Sara
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
257513, H01L 2900
Patent
active
059457244
ABSTRACT:
Shallow trench isolation regions in a semiconductor device are formed by utilizing sacrificial spacers such as polysilicon spacers having a rounded shape to form trench isolation areas. The spacer shape is transferred into a semiconductor substrate during an etching process to define the profile of the trench, resulting in a trench with substantially rounded upper and lower corners in the substrate. An oxide filler material is deposited in the trench and over the substrate to form a covering layer. The covering layer is then polished back to form a filled trench region which electrically isolates active areas in the substrate. The polishing step can be performed by a blanket dry etching procedure, or by a combination of chemical/mechanical planarization and wet etching. The rounded shape of the trench improves the electrical characteristics of the trench such that current leakage is decreased, and also provides a more optimized trench profile for filling the trench with the filler material.
REFERENCES:
patent: 4839306 (1989-06-01), Wakamatsu
patent: 5254218 (1993-10-01), Roberts et al.
patent: 5308784 (1994-05-01), Kim et al.
patent: 5360753 (1994-11-01), Park et al.
patent: 5612242 (1997-03-01), Hsu
patent: 5620930 (1997-04-01), Hey et al.
patent: 5640041 (1997-06-01), Lur et al.
patent: 5643809 (1997-07-01), Lien
patent: 5643822 (1997-07-01), Furukawa et al.
patent: 5661049 (1997-08-01), Lur et al.
patent: 5665632 (1997-09-01), Lur et al.
patent: 5674775 (1997-10-01), Ho et al.
patent: 5753561 (1998-05-01), Lee et al.
patent: 5807789 (1998-09-01), Chen et al.
Li Li
Parekh Kunal R.
Crane Sara
Micro)n Technology, Inc.
LandOfFree
Trench isolation region for semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Trench isolation region for semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Trench isolation region for semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2427076