Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-02-26
2003-05-20
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
Reexamination Certificate
active
06566228
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the fabrication of trench isolations on a semiconductor substrate using polysilicon-assisted fill both with and without a field shield isolation.
2. Discussion of the Related Art
An objective of the semiconductor art is to continually scale down densely packed devices on a semiconductor substrate so as to reduce size and power consumption of the integrated circuits. Devices packed closely together are generally isolated from one another with trench isolations so as to prevent dopants of the active area of one device from migrating to adjacent devices and to avoid parasitic electrical conduction between active areas.
In the art of memory devices, such as in U.S. Pat. No. 5,525,531, issued Jun. 11, 1996, it is known to insert a conductor within a trench isolation for use as a field shield. Memory devices, such as RAMS, DRAMS, and the like, generally comprise an array area and a support area. The array area contains the memory cells and the support area contains the supporting devices required to control addressing of and data transfer into and out of the memory cells. Both areas need trench isolations, but of a different sort. Array devices may be executed as vertical devices, so as to save space. Trenches in the array area need to be deeper, so called “deep isolation trenches”, than those in the support area to protect the vertical devices from one another and to provide enough room for the insertion conductive material that will comprise the field shields. This is because the vertical device will typically be longer than planar devices in the vertical direction by as much as 350 nm. Isolation trenches under these circumstances will be etched deeper than the bottom source/drain contact for isolation. The support trenches have no conductive material inserted at all. Hence, the trenches of the array and support areas are different, but will be formed at substantially the same levels.
Typically, the different trenches of the array and support areas are fabricated by masking off one area while the trenches of the other are built, but this is a time and resource consuming process. It is desirable to utilize a process wherein most of the process steps are executed simultaneously on both the array and support areas, thereby saving manufacturing time and resources.
SUMMARY OF THE INVENTION
Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising providing a first hard mask layer for the array and support areas, said first hard mask comprising mask openings defining trench isolations in the array and support areas, providing deep array trench isolations in the array areas, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said mask openings and deep array trench isolations, etching said conductive material through said first hard mask material down into said semiconductor substrate so as to form support trench isolations, such that both deep array trench isolations and support trench isolations are of equal depth, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.
In another aspect of the method, said substrate material is silicon and said conductive material is polysilicon.
In another aspect of the method, said array area comprises vertical devices.
In another aspect of the method, said conductive element is in electrical contact with said semiconductor substrate.
In another aspect of the method, said conductive element is insulated from said semiconductor substrate.
In another aspect of the method, an electrical contact is provided to said conductive element.
Another aspect of the method further comprises providing an oxide insulator upon inner surfaces of said deep array trench isolations prior to providing said blanketing layer of conductive material.
Another aspect of the method further comprises providing an additional oxide insulator upon inner surfaces defined by said deep array trench isolations.
In another aspect of the method, said conductive element is a field shield.
In another aspect of the method, said field shield is biased.
Disclosed is a method of simultaneously supplying trench isolations for array and support areas of a semiconductor substrate made of a substrate material, the method comprising
providing deep array trench isolations in the array areas and support trench isolations in the support areas, providing an oxide plug within said deep array trench isolations, filling said support trench isolations with oxide, providing a blanketing planarized conductive material layer over both support and array areas sufficient to fill said array and deep array trench isolations, planarizing said conductive material layer to a level substantially equal to said oxide mask, etching said conductive material through said oxide mask material down into said semiconductor substrate so as to bring an upper surface of said conductive material within said deep trench isolations to a level below that of an upper surface of said oxide in said support trench isolations, and wherein a conductive element, comprising a quantity of said conductive material, remains in the bottom of each of said deep array trenches.
In another aspect of the method, said substrate material is silicon and said conductive material is polysilicon.
In another aspect of the method, said array area comprises vertical devices.
In another aspect of the method, said steps of providing an oxide plug within said deep array trench isolations and filling said support trench isolations with oxide is performed by a method comprising the steps of depositing a conformal layer of oxide over said array and support areas of sufficient depth to fill said support trench isolations, and etching back said conformal oxide layer to an extent effective in providing said oxide plug.
In another aspect of the method, said conductive element is insulated from said semiconductor substrate.
In another aspect of the method, an electrical contact is provided to said conductive element.
Another aspect of the method further comprises providing an oxide insulator upon inner surfaces of said deep array trench isolations prior to providing said blanketing layer of conductive material.
Another aspect of the method further comprises providing an oxide insulator upon inner surfaces of said deep array trench isolations prior to providing said conformal oxide layer.
In another aspect of the method, said conductive element is a field shield.
In another aspect of the method, said field shield is biased.
REFERENCES:
patent: 5716868 (1998-02-01), Nagai
patent: 6251734 (2001-06-01), Grivna et al.
patent: 6277707 (2001-08-01), Lee et al.
patent: 6277709 (2001-08-01), Wang et al.
patent: 6306723 (2001-10-01), Chen et al.
Beintner Jochen
Divakaruni Rama
Knorr Andreas
Mandelman Jack A.
Blum David
F. Chau & Associates LLP
International Business Machines - Corporation
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