Trench isolation process

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having air-gap dielectric

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438701, 438713, 438978, 438424, H01L 2176

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active

058800042

ABSTRACT:
A method of providing isolation structure in a semiconductor device having a shallow trench with a rounded top corner is provided for preventing stress centralization as well as current leakage of a device. The method includes the steps of: (a) sequentially forming a pad oxide layer and a silicon nitride layer on a semiconductor substrate; (b) forming an opening in the silicon nitride layer by a first anisotropic etching process, so as to expose an area for forming a shallow trench; (c) performing a wet etching process to remove the pad oxide layer within the opening, the wet etching process removing a portion of the pad oxide layer extending from the opening and under the silicon nitride layer; (d) performing an isotropic etching process to form a hollow with a rounded top corner in the semiconductor substrate, wherein the rounded top corner is located under the silicon nitride layer; and (e) continuously etching the hollow by a second anisotropic etching process using the silicon nitride layer as a mask, thereby forming a shallow trench having a rounded top corner in the semiconductor substrate.

REFERENCES:
patent: 5556797 (1996-09-01), Chi et al.
patent: 5578518 (1996-11-01), Koike et al.
patent: 5683908 (1997-11-01), Miyashita et al.

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