Trench isolation method for CMOS transistor

Details Trench isolation method for CMOS transistor Trench isolation method for CMOS transistor

1996-03-11

1997-03-18

Niebling, John

Fishing, trapping, and vermin destroying

437 34, 437 57, 437 58, 437 63, 437 38, 437 67, 437228, 437 41, H01L 2170

Patent

active

056122420

ABSTRACT:
A method of performing trench isolation in a CMOS transistor, that produces no latch-up and results in an effective isolating structure without using an epitaxial growth process. A field oxide layer is provided on a silicon substrate to isolate an active region. A first conductivity-type well is formed at a predetermined position of the active region. A gate oxide layer, a polysilicon layer and a silicide layer are deposited in sequence. A first gate electrode and a second gate electrode are formed by lithography and etching techniques wherein the first gate electrode is on the well, and the second gate electrode is on the active region outside the well. A silicon nitride layer is deposited and etched back to form spacers on the side walls of the electrodes whereby slits are left between the field oxide layer and the spacers and between adjacent spacers. Trenches are formed by etching the silicon substrate in the slits. An oxide layer is formed to refill the trenches and then etched back to remove the spacers. The well is implanted with impurities of a second conductivity-type to provide second conductivity-type source-drain electrodes by using the first gate electrode as a mask. The active region outside the well is implanted with first conductivity-type impurities to provide first conductivity-type source-drain electrodes, and the process of trench isolation of CMOS transistor is completed.

REFERENCES:
patent: 4729964 (1988-03-01), Natsuaki et al.
patent: 4927777 (1990-05-01), Hsu et al.
patent: 4980306 (1990-12-01), Shimbo
patent: 5525532 (1996-06-01), Kim

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