Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
1999-12-20
2002-12-31
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S501000, C257S506000, C438S221000
Reexamination Certificate
active
06501148
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device and a fabrication method of a semiconductor device, and more specifically, to such a semiconductor device having a trench type element isolation structure and a fabrication method of the same.
2. Description of the Related Art
As element isolation techniques in semiconductor devices, the LOCOS (local oxidation of silicon) method is the most popular element isolation method, in which a thermal oxide film is selectively formed at an element isolation region. However, in the LOCOS method, when an oxide film is formed, an enlargement of an oxide film region called as a “bird's beak” will occur along a transverse direction. As a result, an element forming region becomes narrower than a designed value of the element forming region. Consequently, it is difficult in practice to isolate such element forming regions, the interval of which is shorter than, or equal to 1 micron.
To solve this problem of the LOCOS method, a trench type element isolation structure has been proposed in which a trench is formed in a semiconductor substrate, and then an oxide film is buried into the formed trench. However, such a trench type element isolation structure has the following problem. That is, when the surface of the insulating film buried into the trench formed in the semiconductor substrate becomes lower than the surface of the semiconductor substrate, and a stepped portion is produced at an edge portion of the trench, electric field concentration may occur at the edge portion, and therefore leakage currents may be increased. Under such a circumstance, the two manufacturing methods described below for the trench type element isolation structures having no such stepped portion have been proposed.
(1) JP-A-7-176604 discloses trench type element isolation structure capable of rounding the corners of the silicon substrate in the following manner in order to mitigate the electric field concentration occurring at the edge portion of the buried element isolation region, which is caused by the stepped portion between the surface of the buried element isolation region and the surface of the silicon substrate. That is, after the first oxide film formed on the silicon substrate is side-etched, the third oxide film is formed by thermal oxidation method, which is employed to remove the defect and the like produced in the silicon substrate when the element isolation trench is formed. At this time, the edge portion of the silicon substrate exposed by side-etching the first oxide film is oxidized by way of the thermal oxidation. Also, the volume of the polycrystalline silicon film formed on the first oxide film is expanded by way of the thermal oxidation. As a consequence, the corner of the silicon substrate is rounded. However, even in the trench type element isolation structure, since the corner of the silicon substrate is rounded, there is a problem that the element forming region is narrowed.
(2) JP-A-5-47919 discloses the trench type element isolation structure in which the SiO
2
film buried in the trench groove of the silicon substrate is grown by selective oxidation to form the rounded portion at the edge portion of the element forming region, so that both the bird's beak and the bird's head are formed. However, the trench type element isolation structure is directed to the improvement in the gate withstanding voltage and the leakage current failure in the MOS-type FET, and since both the bird's beak and the bird's head are formed, there is a problem that the element forming region is narrowed.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device having a trench type element isolation structure without forming a bird's beak, and a fabrication method of such a semiconductor device.
To achieve the above-described object, a semiconductor device according to an aspect of the present invention includes a semiconductor substrate in which a trench for element isolation is formed; and an element isolation oxide film buried into the trench in such a manner that the element isolation oxide film is projected from a surface of the semiconductor substrate, wherein the element isolation oxide film has a projection portion above the surface of the semiconductor substrate, the projection portion having a width wider than a width of the trench.
A fabrication method of a semiconductor device according to an aspect of the present invention comprises: a first step of forming a first oxide film on a semiconductor substrate; a second step of forming an easily oxidizable film on the first insulating film; a third step of forming an anti-oxidation insulating film on the easily oxidizable film; a fourth step of patterning the anti-oxidation insulating film; a fifth step of etching the easily oxidizable film, the first oxide film and the semiconductor substrate by using the patterned anti-oxidation insulating film as a mask to thereby form a trench in the easily oxidizable film, the first oxide film and the semiconductor substrate; a sixth step of oxidizing an exposed portion of the easily oxidizable film, which is exposed from a side surface of the trench, to thereby form a second oxide film, and oxidizing an exposed portion of the semiconductor substrate, which is exposed from bottom and side surfaces of the trench, to thereby form a third oxide film; a seventh step of forming a fourth oxide film on the anti-oxidation insulating film in such a manner that the E trench is buried by the fourth oxide film; an eighth step of polishing the fourth oxide film to thereby expose the anti-oxidation insulating film; and a ninth step of removing the anti-oxidation film, the easily oxidizable film and the first oxide film to thereby form an element isolation oxide film containing,at least the second to fourth oxide films.
Alternatively, in the ninth step, only the anti-oxidation film and the easily oxidizable film may be removed.
REFERENCES:
patent: 3962717 (1976-06-01), O'Brien
patent: 5350941 (1994-09-01), Madam
patent: 5433794 (1995-07-01), Fazan et al.
patent: 5554879 (1996-09-01), Poulin
patent: 5753962 (1998-05-01), Jeng
patent: 6005279 (1999-12-01), Luning
patent: 6097076 (2000-08-01), Gonzalez et al.
Fujikake Hideki
Tsuda Nobuyuki
Connolly Bove & Lodge & Hutz LLP
Loke Steven
Owens Douglas W.
United Microelectronics Corporation
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