Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2005-08-23
2005-08-23
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000, C257S510000, C257S513000
Reexamination Certificate
active
06933206
ABSTRACT:
An isolation trench formed in a semiconductor substrate and is filled with at least one insulating liner layer that is deposited along sidewalls and a bottom region of the isolation trench and with at least one silicon liner layer that is deposited atop the insulating liner layer. An upper portion of the insulating liner layers are removed, and the silicon liner layers are removed. A remaining portion of the trench is filled with another insulating layer.
REFERENCES:
patent: 5116779 (1992-05-01), Iguchi
patent: 6596607 (2003-07-01), Ahn
patent: 6812115 (2004-11-01), Wieczorek et al.
Beintner Jochen
Knorr Andreas
Everhart Caridad
Slater & Matsil L.L.P.
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