Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Bipolar transistor
Reexamination Certificate
2000-08-04
2003-12-02
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Bipolar transistor
C257S205000
Reexamination Certificate
active
06657242
ABSTRACT:
TECHNICAL FIELD
The present invention relates to bipolar semiconductor devices, in particular bipolar transistors and semiconductor diodes, which are electrically isolated or confined by trenches.
BACKGROUND
When manufacturing bipolar transistors one can use a highly doped inner layer, a bottom diffusion or “buried layer”. The purpose of this bottom diffusion layer is to reduce the collector series resistance for NPN-transistors and to serve as a base connection for corresponding lateral PNP-transistors. By introducing a highly doped bottom diffusion, in the cases usually of type N+, the performance of the components can be considerably improved. Such a bottom diffusion, which is produced before an epitaxial layer is grown on the silicon plate, on which the components are built, is then connected from the component surface through a region comprising a deep diffusion of type N+. In this region a doping has first been made at the surface and then the atoms introduced in the doping process have been made to diffuse deeply down into the silicon plate by a suitable heat treatment. The individual components manufactured on the same silicon plate can be isolated from each other by areas comprising deep P-diffiusions, which extend through the epitaxial layer down to the inner or interior material of the silicon plate, i.e., the substrate, which in these cases is silicon of P-type.
For the NPN-transistor shown in
FIG. 1
, the highly doped inner layer or bottom diffusion layer
1
is produced by diffusion from the surface of the P-substrate
3
, before the epitaxial layer
5
of N-type is grown on the silicon plate
3
. The bottom diffusion
1
is located under the whole active area
7
of the collector and is intended to reduce the series resistance of the collector connection. This series resistance is for NPN-transistors normally determined by a rather thin region of the weakly doped silicon layer of N-type, which forms the active collector area
7
. By shunting in this way the weakly doped, very collector layer
7
by a highly doped bottom diffusion
1
which has a lower resistivity and is type N+ for NPN-transistors, component performance can be considerably improved, i.e., the resistance between the exterior collector contact
9
and the active portion
7
of the collector is reduced. The bottom diffusion
1
of type N+ is then connected from the surface of the component through a deep localized diffusion
11
of type N+ for obtaining a so called collector plug, the upper surface of which is connected to the exterior collector contact
9
. The bottom diffusion layer
1
is furthermore located so that it extends under all of the active area of the transistor. It thus extends under all of the very base in the P-layer
13
and under the emitter layer
15
, which is doped to N+. The individual transistors are isolated from each other by deep localized diffusion regions
17
of type P+, which extend through the epitaxial layer
5
down to the substrate
3
, which, as has already been indicated, in the standard case is P-type silicon.
In some IC-applications also lateral bipolar transistors of PNP-type are also used, see
FIGS. 2
a
and
2
b
. In this case the bottom diffusion layer
21
, which also in this case is of type N+, constitutes a connection to the very base
23
, which is an epitaxial N-layer. In order to further reduce the contact resistance to the base
23
here a deep localized diffusion
25
of type N+ is also used, which extends from the surface of the component down to the bottom diffusion
21
. The bottom diffusion
21
also in this case extends under all of the active area of the transistor, i.e., under the very collector
27
of type P+ and all of the emitter
29
, which is also doped to P+. The bottom diffusion
21
is as above produced by diffusion from the surface of the P-substrate
31
. In the plan view of
FIG. 2
b
the generally square layout of the PNP-transistor appears, the various regions or areas forming square structures or square frame-like or annular structures.
The advantages of using a bottom diffusion in this case comprise:
i) that the base resistance is reduced
ii) that the concentration of holes in the connection intermediate region or junction between the epitaxial layer
23
which is of N-type and the substrate
31
of P-type is reduced. Thereby, the current gain is reduced for the vertical-parasitic PNP-transistor, which is formed by substrate-base-emitter or substrate-base-collector.
In that way a better current amplification and a better frequency behavior are obtained in the PNP-transistor.
Also in this case the components can be isolated from each other by deep P-diffusions, not shown, which extend through the epitaxial layer
23
down to the substrate
31
, which is P-type silicon.
When manufacturing high frequency transistors, for which one wants to obtain very high performance, it is common to replace the isolating, deep localized diffusions
17
of type P+, as mentioned above in conjunction with FIG.
1
and intended for isolating individual components such as transistors, by ditches etched deeply down into the silicon having at least in their upper portions substantially vertical side walls, so called “trenches”, see FIG.
7
and e.g. P. C. Hunt and M. P. Cooke, “Process HE: A highly advanced trench isolated bipolar technology for analogue and digital applications”, Proc. of IEEE 1988, Custom & Integr. Circuits Conf., N.Y., May 16-19. Thereby, the capacitance between the bottom diffusion and the substrate can be considerably reduced at the same time as the dimensions of the individual transistor can be reduced, in particular its extension in lateral directions, i.e., in directions along the surface of the silicon plate, and a better isolation mutually between components is obtained.
In directions along the surface of the structure in all these designs a lot of area is consumed for producing both the collector plug and the base connection diffusion, respectively, and devices for isolating transistors from each other.
U.S. Pat. No. 5,003,365 discloses a bipolar transistor of NPN-type. The connection to the N-collector area 6 is obtained by the fact that a trench, which is isolated by means of oxide on its sidewalls, is filled with electrically conducting polysilicon of type N+. A hole exists in the oxide layer in a sidewall of a trench, from which a limited region has been diffused from the filling material in the trench. This region obtains an approximatively semi-cylindrical shape, having the flat surface extending along a diameter plane located at the sidewall of the trench. Producing this hole in the sidewall oxide requires a plurality of extra processing steps. The transistor takes, owing to the connection of the collector through a trench, a small area on the substrate surface. By the fact that furthermore all of the width of the trench is used for connecting, the isolating function thereof is reduced and can result in undesired capacitances to the substrate.
In U.S. Pat. No. 5,496,745 a bipolar transistor is disclosed having a bottom diffusion 22 located under the active collector layer 23, where the bottom diffusion is directly connected to a contact plug 35 outside trenches, which define the collector layer. The transistor takes a large area of the substrate surface.
In U.S. Pat. No. 5,187,554 which corresponds to the published European patent application 0 303 435 a bipolar NPN-transistor having a buried collector region is disclosed. In FIGS. 3-5 it is illustrated how the collector region is connected to the exterior electrical contact through a recess made at least partly in an isolating trench, the recess being made at the inner sidewall of the trench. This construction results in a reduced area of the transistor produced and reduced parasitic capacitances.
SUMMARY
It is an object of the present invention to provide a trench isolated transistor having improved performance.
In particular it is an object of the present invention to provide a trench isolated tr
Lindgren Anders
Norström Hans
Tylstedt Ola Knut
Burns Doane Swecker & Mathis L.L.P.
Owens Douglas W.
Telefonaktiebolaget LM Ericsson (publ)
Thomas Tom
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