Trench IGBT

Details Trench IGBT Trench IGBT

2002-04-25

2004-01-27

Fahmy, Wael (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Emitter region feature

C257S330000

Reexamination Certificate

active

06683331

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to Insulated Gate Bipolar Transistors (IGBTs) and more specifically relates to an IGBT employing a trench topology.
BACKGROUND OF THE INVENTION
IGBTs are well known and are frequently implemented with a planar cellular or stripe topology. These devices have an inherent JFET which increases the device on-resistance R
DSON
and, thus the forward voltage drop V
ce(ON)
. Further, such devices have an inherent four layer parasitic thyristor structure which will latch on if the NPN transistor of the thyristor turns on.
It is known that IGBTs can be made with a trench topology which eliminates the inherent JFET of the planar device. However, trench IGBTs still have the inherent four layer device whereby, if the inherent NPN transistor in the four layer device turns on (if the current through R
B′
is sufficiently high), the device will latch on. It is also desirable to reduce the saturation current of the device without increasing the value of R
B′
.
It has further been found that trench IGBTs tend to be “fragile,” that is, they can fail when switching an inductive load. This is sometimes termed a low safe operating area (SOA) under reverse bias. This problem again is aggravated by an increased R
B′
BRIEF DESCRIPTION OF THE INVENTION
In accordance with the invention, a novel trench IGBT structure and process for its manufacture is provided, creating a non-punch through (NPT) IGBT having a reduced R
B′
, a reduced saturation current, a low threshold voltage V
T
and an enlarged SOA. More specifically, a novel structure is provided having a deep emitter diffusion which is very narrow (of small lateral extent) to reduce R
B′
. Further, a very deep P channel diffusion is employed between spaced trenches to create a very long inversion channel. Thus, when the device goes into avalanche, the path for hole current under the emitter has a reduced lateral extent, reducing R
B′
; and the trench is very deep (about 8 microns) so that the P region adjacent the channel can support reasonable voltage and the N
−
body concentration and depth can be optimized. The increased depth of the emitter along the trench controls threshold voltage since it permits the use of a very deep P
+
region without the danger of its encroaching into the channel (which would increase V
T
). Finally, a helium implant may be employed for lifetime killing in only the P well.
Further, the device of the invention may be built in float zone silicon and no epitaxial layer is needed, with a weak anode structure being employed as in copending application Ser. No. 09/565,922, filed May 5, 2000 in the names of Richard Francis and Chiu Ng.


REFERENCES:
patent: 5631494 (1997-05-01), Sakurai et al.
patent: 6118150 (2000-09-01), Takahashi
patent: 2001/0023960 (2001-09-01), Soga et al.
patent: 04317375 (1992-11-01), None

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