Trench etching in an integrated-circuit semiconductor device

Details Trench etching in an integrated-circuit semiconductor device Trench etching in an integrated-circuit semiconductor device

1995-04-20

1997-04-15

Breneman, R. Bruce

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having air-gap dielectric

438430, 438426, 438433, 438702, H01L 21467

Patent

active

056209304

ABSTRACT:
In the manufacture of semiconductor integrated circuit devices, semiconductor regions such as, e.g., doped regions or tubs are separated by an etched trench which is self-aligned with respect to such regions on account of the presence of an etch-resistant layer overlying the regions during etching. In accordance with preferred processing of the invention a first layer is formed alongside the trench to be etched, a spacer second layer is formed alongside the edge of the first layer, and a third layer is formed abutting the spacer. The spacer is etched away while first and third layers remain in place, and the trench is etched in the space between the first and third layers. A preferred etchant comprises CF.sub.3 Br and oxygen.

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patent: 4786359 (1988-11-01), Stark et al.
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European Search Report dated Aug. 19, 1991.

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