Trench DRAM cell with different insulator thicknesses

Details Trench DRAM cell with different insulator thicknesses Trench DRAM cell with different insulator thicknesses

1988-10-04

1991-06-04

Larkins, William D.

357 55, H01L 27108

Patent

active

050218425

ABSTRACT:
A DRAM having the capacitors of memory cells formed by utilizing moats is disclosed. The moats are provided in a semiconductor substrate independently for the respective capacitors by anistropic dry etching, and they serve to increase the capacitances of the capacitors without increasing the areas which they occupy. The greater part of each capacitor is buried in the moat. The capacitors are electrically isolated from the semiconductor substrate, and the semiconductor substrate is not used as the electrodes of the capacitors. The capacitor consists of first and second polycrystalline silicon layers, and an insulator film formed therebetween. The first polycrystalline silicon layer serves as a lower electrode electrically isolated from the semiconductor substrate. This first polycrystalline silicon layer is formed independently for each capacitor, and it is connected to the source or drain region of the MISFET of the memory cell. The second polycrystalline silicon layer and the insulator film are common to the memory cells in an identical memory cell array, and are unitarily formed. A fixed potential is applied to the second polycrystalline silicon layer.

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patent: 4119772 (1978-10-01), Natori
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patent: 4432006 (1984-02-01), Takei
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Sunami et al., IEEE International Electron Dev. Meeting; Tech. Digest, pp. 806-808, Dec. 12, 1982.
IBM TDB, Dec. 1980, pp. 2863-2865.
IBM TDB, Jul. 1982, pp. 593-596.
Electronics, Dec. 15, 1982, pp. 86 and 88 (Sunami).

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