Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-03-07
2001-12-04
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C257S510000, C438S218000, C438S296000, C438S435000
Reexamination Certificate
active
06326283
ABSTRACT:
BACKGROUND
The present invention concerns the fabrication of integrated circuits and pertains particularly to trench-diffusion corner rounding in a shallow-trench (STI) process.
In fabricating integrated circuits, various processes are used to form field oxide. For example, a local oxidation of silicon (LOCOS) process is often used to form field oxide regions. In a LOCOS process, a layer of pad oxide is formed. On top of the pad oxide, a layer of nitride is formed. The nitride is patterned and etched. Field oxide is grown on the substrate at places where the nitride has been etched to expose the substrate. The nitride and pad oxide are then removed.
Shallow trench isolation (STI) is gradually replacing conventional LOCOS process for the formation of an isolation structure as technology is evolving to submicron geometry. STI has various advantages over the conventional LOCOS process. For example, STI allows for the planarization of the isolation structure. This results in better control of critical dimension (CD) when defining a gate stack of a transistor. Better control of CD when defining the gate stack results in better control of CD in further processing steps which occur after the gate stack is defined.
In a typical STI process, a buffer oxide of 10 to 20nm is thermally grown on wafer substrate. A nitride of approximately 200nm is deposited and then patterned with lithography and etched down to silicon. An etch that is selective to silicon (etches mostly silicon) is then used to etch a trench into the silicon. A liner oxide is thermally grown to anneal out any damage to the silicon and passivate the silicon. Next, an oxide that is considerably thicker than the trench depth is deposited. The wafer is then subjected to a chemical-mechanical (CMP) polishing that stops when it reaches the nitride. The nitride is then stripped, along with the buffer oxide underneath, thereby forming the shallow trench isolation.
For the above-described STI processing scheme, the sharp corner where the trench side wall meets the silicon surface causes many problems with device performance, yield, and reliability. See, for example, P. Sallagoity, et al.“Analysis of Width Edge Effects in Advanced Isolation Schemes for Deep Submicron CMOS Technologies”, IEEE Trans. Elect. Devices. Vol. 43, No. 11, November 1996. The problems include a parasitic transistor at the corner that has a lower threshold voltage, and thinner gate oxide at the corner, resulting in immediate device failure or reliability issues.
SUMMARY OF THE INVENTION
In accordance with the preferred embodiment of the present invention, an isolation structure on an integrated circuit is formed using a shallow trench isolation process. A layer of buffer oxide is formed on a substrate. A layer of nitride is formed on the layer of buffer oxide. The layer of nitride and the layer of buffer oxide are patterned to form a trench area. An oxidation of the substrate is performed to provide for round corners at a perimeter of the trench area. The substrate is then etched to form a trench within the trench area.
In the preferred embodiment processing continues by growing a layer of liner oxide within the trench. The trench is filled with oxide. A chemical-mechanical polish of the oxide is performed down to the nitride layer. The nitride layer is then removed.
The rounded corners at the perimeter of the trench increases the threshold voltage of the parasitic transistor at the corners of the trench. The rounded corners also allow for oxide at the corners to be thick enough to overcome immediate device failure and reliability issues.
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Chatterjee et al., A shallow trench isolation using LOCOS edge for preventing corner effects for 0.25/0.18 &mgr;m CMOS technologies and beyond, International Electronic Devices Meeting, 1996, 829-832.*
P. Sallagoity, et al. “Analysis of Width Edge Effects in Advanced Isolation Schemes for Deep Submicron CMOS Technologies”, IEEE Trans. Elect. Devices. vol. 43, No. 11, Nov. 1996.
Laparra Olivier
Liang Victor
Rubin Mark
Elms Richard
VLSI Technology Inc.
Wilson Christian D.
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