Trench and gate dielectric formation for semiconductor devices

Details Trench and gate dielectric formation for semiconductor devices Trench and gate dielectric formation for semiconductor devices

1998-08-03

2001-06-12

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S435000, C438S437000, C438S296000, C148SDIG005

Reexamination Certificate

active

06245638

ABSTRACT:

FIELD OF THE INVENTION
The present invention is, in general, directed to a semiconductor device having trench isolation regions and methods for making the semiconductor device. More particularly, the present invention relates to method of forming trench and gate dielectric layers of a semiconductor device with a trench isolation region.
BACKGROUND OF THE INVENTION
Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor (MOS) transistors, complimentary MOS (CMOS) transistors, bipolar transistors, bipolar CMOS (BiCMOS) transistors, etc.
Each of these semiconductor devices generally include a semiconductor substrate on which a number of active devices are formed. The particular structure of a given active device can vary between device types. For example, in MOS transistors, an active device generally includes source and drain regions and a gate electrode which modulates current between the source and drain regions.
A typical MOS semiconductor device
50
generally includes a semiconductor substrate
52
on which a gate electrode
54
is disposed, as shown in FIG.
1
. The gate electrode
54
, which acts as a conductor, receives an input signal to control operation of the device. Source and drain regions
56
are typically formed in regions of the substrate adjacent the gate electrode by heavily doping these regions with a dopant material of a desired conductivity. The conductivity of the doped region depends on the type of impurity used to dope the region. The collective term source/drain region is used herein to generally describe an active region used for the formation of either a source or drain.
A channel region
58
is formed in the semiconductor substrate beneath the gate electrode
54
and between the source and drain regions
56
. The channel is often lightly doped with a dopant material having a conductivity type opposite to that of the source and drain regions. The gate electrode is generally separated from the substrate by a gate insulating layer
60
, typically an oxide layer such as SiO
2
. The gate insulating layer is provided to restrain current from flowing between the gate electrode
54
and the source, drain or channel regions
56
,
58
.
MOS devices typically fall in one of two groups depending the type of dopant materials used to form the source, drain and channel regions. The two groups are often referred to as n-channel and p-channel devices. The type of channel is identified based on the conductivity type of the channel which is developed under the transverse electric field. In an n-channel MOS (NMOS) device, for example, the conductivity of the channel under a transverse electric field is of the conductivity type associated with n-type impurities (e.g., arsenic or phosphorous). Conversely, the channel of a p-channel MOS (PMOS) device under the transverse electric field is associated with p-type impurities (e.g., boron).
Semiconductor devices, like the ones mentioned above, are used in large numbers to construct most modem electronic devices. As a larger number of such devices are integrated into a single silicon wafer, improved performance and capabilities of electronic devices can be achieved. In order to increase the number of semiconductor devices which may be formed on a given surface area of a substrate, the semiconductor devices must be scaled down (i.e., made smaller). This is accomplished by reducing the lateral and vertical dimensions of the device structure.
One important step in the formation of semiconductors is the process of forming isolation regions, i.e., regions in the substrate which are used to electrically isolate adjacent active devices. Two common techniques for isolating active devices on a semiconductor substrate are LOCOS (for LOCal Oxidation of Silicon) isolation and trench isolation. Trench isolation techniques, and many LOCOS isolation techniques, generally involve the formation of a trench in the substrate. The formation of the trench typically begins by forming a pad oxide layer and then a nitride layer on the substrate. The pad oxide layer and the nitride layer are patterned and etched to expose the substrate and define the regions. The exposed substrate is then etched to form the trench. In most cases, an oxide layer is thermally grown in the trench to form at least part of the isolation region. A dielectric material is then deposited over the grown oxide layer to fill the trench. A more detailed discussion of LOCOS and trench isolation techniques can be found in S. Wolf, Silicon Processing For The VLSI Era, Vol. 2: Processing Integration, Ch. 2, pp. 28-58, 1990.
One concern with trench isolation is the uniformity of the trench/substrate interface, particularly near the upper surface of the substrate (i.e., the trench edge). The formation of an oxide layer by thermal oxidation utilizes a portion of the substrate from the sidewalls and bottom of the trench. This typically results in rounded corners and edges of the trench. Although this is often useful for the bottom corners of the trench, as it may permit more uniform dielectric material deposition in the trench, the rounding of the upper edges of the trench can affect device properties due to non-uniformity. In addition, silicon nitride deposits may be formed under the pad oxide layer during the thermal oxidation of the trench. This occurs as nitrogen from the nitride layer over the pad oxide layer diffuses through the pad oxide and reacts with the silicon substrate. The presence of these silicon nitride deposits can result in a weakened or thinner gate insulating layer that is formed, for example, by oxidation of the substrate adjacent to the trench. There is a need to develop new-methods of forming trench isolation structures and gate insulating layers that provide adequate, and even improved, isolation of neighboring semiconductor devices and/or isolation of the gate from the substrate.
SUMMARY OF THE INVENTION
Generally, the present invention relates to the formation of semiconductor devices that include trench isolation. One embodiment is a method of making a semiconductor device. A masking layer is formed over a substrate to expose a field region and cover an active region of the substrate. A trench is formed in the field region and filled with dielectric material. The substrate is oxidized to form a first sacrificial layer in the active region adjacent to the trench. The first sacrificial layer is removed. A second sacrificial layer is formed in the active region adjacent to the trench by oxidizing the substrate. The second sacrificial dielectric layer is removed. This often provides an improved surface for the subsequent formation of the gate insulating layer and gate electrode.
Another embodiment is another method of making a semiconductor device. A masking layer is formed over a substrate to expose a field region and cover an active region of the substrate. A trench is formed in the field region and filled with dielectric material. A nitrided oxide layer is formed over the active region of the substrate adjacent to the trench. The nitrided oxide layer is then removed. This also often provides an improved surface for the subsequent formation of the gate insulating layer and gate electrode.
Yet another embodiment is another method of making a semiconductor device. A masking layer is formed over a substrate to expose a field region and cover an active region of the substrate. A trench is formed in the field region. The trench is thermally oxidized in a nitrogen-bearing ambient to form a nitrided oxide liner layer. This often provides a trench that is resistant to diffusion of dopant material into the trench.
The above summary of the present invention is not intended to describe ea

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