Trellis demapper of a convolutional decoder for decoding pragmat

Pulse or digital communications – Receivers – Particular pulse demodulator or detector

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371 431, 371 434, H03M 1312

Patent

active

057402035

ABSTRACT:
A memory efficient trellis demapper for demapping 8-PSK and 16, 32, 64 128 and 256-QAM trellis codes contains respective I-channel, Q-channel and remapper random access memory (RAM), an 8-PSK demapper logic network, and a selector switch. Each RAM includes a lookup table selectively programmed for each QAM code. The I-channel RAM and the Q-channel RAM forward their respective outputs through the switch as the trellis demapper output in response to an even power of 2 (i.e., 16, 64 or 256) QAM trellis code being selected. In response to an odd power of 2 (i.e., 32, 128) QAM trellis code being selected, the respective outputs of the I and Q channel RAMs are input to the remapper RAM, and the remapper RAM output is conveyed via the switch as the trellis demapper output. When an 8-PSK trellis code is selected, the output of the 8-PSK demapper logic network is conveyed via the switch as the trellis demapper output.

REFERENCES:
patent: 5469452 (1995-11-01), Zehavi
Preliminary Data Bulletin for the Q1875 Trellis Decoder, Qualcomm Incorporated, VLSI Products Division, San Diego, CA.
Development of Variable Rate Viterbi Decoder and its Performance Characteristics, Proceedings of the 6th ICDSC Conference, Phoenix, Arizona, 1983.
A 25 MHz Viterbi FEC Codec by Kerr et al., IEEE 1990 Custom Integrated Circuits Conference.
Practical Coding for QAM Transmission of HDTV by Heegard et al., IEEE Journal on Selected Areas in Communications, Jan. 1993.
Forward Error Correction Applied to Intelsat IDR Carriers by Morley, International Journal of Satellite Communications, vol. 6, 1988.
45 Mbps Viterbi Decoder, STEL-2060, Stanford Telecommunications, Sunnyvale, CA, 1992, 1993, pp. 1-15.

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