Television – Plural transmitter system considerations
Reexamination Certificate
1998-06-08
2001-03-13
Peng, John K. (Department: 2714)
Television
Plural transmitter system considerations
C348S607000, C348S608000, C348S725000, C348S470000, C348S426100, C375S341000, C375S296000, C375S346000
Reexamination Certificate
active
06201563
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an apparatus for receiving and decoding a digital video broadcast signal. More specifically, this invention relates to a device with a new trellis code modulation decoder structure which demonstrates an improved performance in the presence of NTSC co-channel interference.
2. Description of the Related Art
A Digital Television System (DTS) standard was recently prepared by the Advanced Television Systems Committee (ATSC). The DTS standard outlines various system characteristics of the Advanced Television (ATV) system proposed for use in the U.S., and Annex D in particular specifies the Radio Frequency (RF) transmission subsystem for the DTS standard. The RF transmission subsystem performs amplitude and vestigial sideband modulation (VSB) in two modes: a terrestrial mode (8-level VSB, or simply 8 VSB)) and a high data rate mode (16-level VSB, or simply 16 VSB). Since no trellis code modulation is employed in the 16 VSB mode, the discussion hereafter will focus on the 8 VSB mode.
Turning now to the figures,
FIG. 1
shows one embodiment of a ATV transmitter
100
. The ATV transmitter comprises a data randomizer
102
, a Reed-Solomon encoder
104
, an interleaver
106
, a trellis encoder
108
, a sync word insertion module
110
, a pilot insertion module
112
, a VSB modulator
114
, and a radio-frequency (RF) up-converter
116
. The ATV transmitter
100
receives a digital audiovisual signal, e.g. an MPEG bitstream, in the form of 188-byte data packets. The first byte is a synchronization byte, and the remaining 187 bytes are payload data.
Data randomizer
102
drops the synchronization byte and changes each remaining byte value according to a known pattern of pseudo-random number generation in order to eliminate repetitious patterns and provide the data with a completely random noise-like character. Reed-Solomon encoder
104
encodes the 187 randomized bytes to add 20 redundancy bytes to enable future error correction of up to 10 byte errors. Interleaver
106
re-orders the encoded bytes to intermix the byes from different packets and thereby provide resistance to burst errors (since all the bytes for a given packet are no longer located in a short time interval). Trellis encoder
108
provides further encoding and modulation, and is discussed further below. At the trellis encoder output, 328symbols are produced for every 187 input bytes. Sync word insertion module
110
pre-pends a 4-symbol segment synchronization word to each group of 328 symbols to form a 332 symbol data segment, and further inserts a field synchronization segment for every set of 312 data segments to form a 313 segment data field. Pilot insertion module
112
provides a DC offset to all the symbols. The DC offset will appear as a carrier tone in the modulated signal. VSB modulator
114
modulates the symbols from module
112
onto an intermediate frequency (IF) carrier in 8-level amplitude-modulated vestigial-sideband form, and RF up-converter 116 moves the IF signal into the assigned frequency channel, and amplifies and filters the output signal before supplying it to a transmit antenna.
The trellis encoder
108
actually consists of 12 identical trellis encoders
202
-
224
as shown in FIG.
2
. The bytes coming into the trellis encoder
108
are divided into two-bit symbols, and each trellis encoder
202
-
224
receives every 12th two-bit symbol, i.e. encoder
202
operates on the 0th, 12th, 24th, 36th, . . . two-bit symbols, encoder
204
operates on the 1st, 13th, 25th, 37th, . . . two-bit symbols, and so on. At the output of the encoders
202
-
224
, a three-bit symbol is provided for each two-bit input symbol. During insertion of the segment synchronization byte, the output multiplexer of
FIG. 2
is advanced by four symbols, although the state of the encoders is not advanced.
FIG. 3
shows one embodiment of trellis encoder
202
. The most-significant bit (MSB) of the two-bit word is “precoded” using delay element
302
and XOR gate
304
to produce mapper input Z
2
. The least-significant bit (LSB) is convolutionally encoded using delay elements
306
,
308
and XOR gate
310
to produce mapper inputs Z
1
, Z
0
. The three mapper inputs may be converted to a signal amplitude immediately by a mapper
312
, but typically Z
2
, Z
1
, and Z
0
are simply forwarded as a three bit symbol and converted later by VSB modulator
114
.
FIG. 4
shows a second embodiment of trellis encoder
202
. In this embodiment, the convolutional encoder formed by delay elements
406
,
408
and XOR gate
410
, is a moving-window encoder rather than a feedback encoder. The correspondence between input bits and output sequences is somewhat altered, but the overall code properties are the same. Either encoder may be employed.
During the transition period from the National Television Standards Committee (NTSC) standard to the DTS standard, many ATV transmissions will take place in channels which are shared by NTSC transmissions in neighboring broadcast regions. It is desirable to provide a system with increased immunity to co-channel interference from these NTSC transmissions.
FIG. 5
shows one embodiment of an ATV receiver
500
which includes provisions for screening out interfering NTSC transmissions. Receiver
500
comprises tuner
502
, IF module
504
, NTSC rejection filter
506
, equalizer
508
, phase tracker
510
, trellis decoder
512
, de-interleaver
514
, Reed-Solomon decoder
516
, and de-randomizer
518
.
Tuner
502
receives all the signals in a designated frequency band from the receiver antenna, and downmixes a selected channel to IF (at 44 MHz). IF module
504
filters out undesired adjacent channels using a square-root raised-cosine bandpass filter, and locks on to the carrier tone using a narrowband frequency-and-phase locked loop (FPLL). NTSC rejection filter
506
is a “comb” filter with nulls near the standard NTSC luminance, color, and audio carrier frequencies to screen out interference from NTSC transmissions. Filter
506
may be switched in or out of the processing pipeline as needed.
Equalizer
508
is a moving-window adaptive equalizer that operates to remove any linear distortions (e.g. spectrum tilt, multi-path echo) from the received signal and thereby maximize the “eye openings” in the equalized signal. Phase tracker
510
is a wide-band first-order tracking loop that removes any remaining phase noise not tracked by the FPLL carrier recovery loop. The phase tracker
510
operates independently of the preceding modules.
Trellis decoder
512
operates according to the Viterbi algorithm to demodulate the data, in a manner discussed further below. De-interleaver
514
reverses the operation of interleaver
106
to gather the dispersed bytes from Reed-Solomon encoded packets back together, and Reed-Solomon decoder
516
decodes the packets, providing error correction as needed. The de-randomizer then reverses the operation of randomizer
102
to produce the original data packets.
FIG. 6
shows that trellis decoder
512
is actually comprised of 12 identical trellis decoders
602
-
624
. The trellis decoders each process every 12th signal sample and form a two-bit symbol decision for each signal sample. To drop the synchronization bytes, the input multiplexer continues to advance during synchronization intervals, but the processing by the trellis decoders
602
-
624
is frozen. The two-bit symbol decisions are re-assembled into bytes by the output multiplexer before being forwarded to the de-interleaver
514
.
FIG. 7
illustrates the modes of operation of the trellis decoder
602
. Trellis decoder
602
implements a 4-state trellis decoder
702
when the NTSC rejection filter is not used. When the NTSC rejection filter is used, an 8-state trellis decoder
704
is implemented. The effect of the comb filter is indicated by the presence of the delay element
706
and sum element
708
, which adds additional state dependence to valid received signal sequences. The delay element
706
and summer
708
are shown for explanatory
Conley, Rose & Tayon Law Firm
Desir Jean W.
LSI Logic Corporation
Peng John K.
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