Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2002-12-30
2003-11-25
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S773000, C257S738000
Reexamination Certificate
active
06653728
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to trays for semiconductor packages, and more particularly, to a tray for storage and transportation of ball grid array (BGA) semiconductor packages.
BACKGROUND OF THE INVENTION
A BGA semiconductor package is characterized in mounting at least a chip on a surface of a substrate, and implanting a plurality of solder balls on an opposing surface of the substrate; these solder balls act as input/output connections of the semiconductor package to allow the chip to be electrically connected to an external device such as printed circuit board (PCB) via the solder balls.
Generally, a plurality of fabricated BGA semiconductor packages are simultaneously stored or transported by means of a tray to be subject to subsequent processes such as functional tests. As semiconductor packages are structured more complicated and incorporated with more delicate components or elements, they may be more easily damaged by external impact or influence such as mechanical shock, and therefore, the design for a tray is critical for allowing semiconductor packages to be properly supported and protected by the tray so as to assure structural integrity of the semiconductor packages.
U.S. Pat. Nos. 5,400,904 and 6,116,427 disclose a tray
1
, as shown in
FIG. 5A
, having a body
10
formed with a plurality of recessed cavities
11
for receiving semiconductor packages
12
therein respectively, and the recessed cavities
11
are each dimensioned to properly accommodate the corresponding semiconductor package
12
. Moreover, an inner side wall
110
of the recessed cavity
11
is formed with a plurality of flanges
13
for supporting the semiconductor package
12
, wherein a substrate
14
of the semiconductor package
12
is implanted on a surface thereof with a plurality of solder balls
15
, and the semiconductor package
12
is received in the recessed cavity
11
in a manner that the solder balls
15
are directed toward a bottom surface
111
of the recessed cavity
11
and the flanges
13
come into contact with a peripheral portion of the surface of the substrate
14
having the solder balls
15
without interfering with arrangement of the solder balls
15
, such that the semiconductor package
12
can be positioned within the recessed cavity
11
and supported by the flanges
13
of the tray
1
.
However, as the peripheral portion of the substrate
14
in contact with the flanges
13
of the above tray
1
is quite narrow (e.g. 0.7 mm or even smaller), by dimensional inaccuracy of the flanges
13
in fabrication, as shown in
FIG. 5B
, the flanges
13
may possibly abut against or press on nearby solder balls
15
that may be damaged with cracks, thereby undesirably affecting structure and electrical-connection quality of the semiconductor package
12
. Moreover, the semiconductor package
12
received in the recessed cavity
11
of the tray
1
is merely supported by the flanges
13
; during movement of the tray
1
or performance of subsequent processes such as functional tests, the semiconductor package
12
may be shifted in position or dislocated to thereby adversely affect process or test performance, and this unsatisfactory positioning problem may also cause structural damage to the semiconductor package
12
due to impact, thereby degrading yield of package products.
Other related prior arts such as U.S. Pat. Nos. 5,890,599 and 6,264,037 similarly disclose a tray for semiconductor packages, but still fail to solve the above structural damage problem in terms of solder-ball cracking and unsatisfactory positioning for the semiconductor packages.
Therefore, the problem to be solved herein is to provide a tray for semiconductor packages, so as to assure structural integrity of the semiconductor packages accommodated by the tray.
SUMMARY OF THE INVENTION
A primary objective of the present invention is to provide a tray for ball grid array (BGA) semiconductor packages for accommodate a plurality of semiconductor packages, which can maintain structural integrity of the semiconductor packages without damaging solder balls thereof, and assure electrical-connection quality of the semiconductor packages.
Another objective of the invention is to provide a tray for BGA semiconductor packages for accommodate a plurality of semiconductor packages, which can securely position and support the semiconductor packages.
In accordance with the above and other objectives, the present invention proposes a tray for BGA semiconductor packages, with a surface of a BGA semiconductor package being defined with a ball-implanting area where a plurality of solder balls are array-arranged and a non-ball-implanting area free of the solder balls, the tray comprising: a body having an upper surface and a lower surface opposed to the upper surface, the upper surface being formed with a plurality of downwardly recessed cavities, for allowing the semiconductor packages to be received in the recessed cavities with the surfaces of the semiconductor packages having the solder balls facing toward bottom surfaces of the recessed cavities; at least a protruding portion formed on the bottom surface of each of the recessed cavities, and corresponding in position to the non-ball-implanting area of the surface of the corresponding semiconductor package, so as to allow the protruding portion to support the semiconductor package received in the corresponding recessed cavity; and at least a positioning portion formed on the lower surface of the body, and corresponding in position to a gap between an inner side wall of each of the recessed cavities and the semiconductor package received in the corresponding recessed cavity; when the trays incorporated with the semiconductor packages are vertically stacked, a positioning portion of an upper tray is engaged with a gap between an inner side wall of a recessed cavity and a semiconductor package received in the recessed cavity of a lower tray, so as to securely position the semiconductor package accommodated by the lower tray.
In the use of the above tray for storage and transportation of a plurality of semiconductor packages, the semiconductor packages are respectively received in recessed cavities of the tray, with non-ball-implanting areas thereof free of solder balls being supported by protruding portions formed on bottom surfaces of the recessed cavities; this does not require the use of flanges formed on an inner side wall of a recessed cavity of a conventional tray to support a quite narrow peripheral portion of a chip carrier (such as a substrate) of a semiconductor package received in the recessed cavity, thereby preventing cracks of solder balls being pressed by the flanges. Therefore, structural integrity and electrical-connection quality of the semiconductor packages can be assured through the use of the above tray for accommodating the semiconductor packages. Moreover, when the trays are vertically stacked, a positioning portion of an upper tray is engaged with a gap between an inner side wall of a recessed cavity and a semiconductor package received in the recessed cavity of a lower tray, so as to securely position the semiconductor packages accommodated by the lower tray without the occurrence of positional shift or dislocation of the semiconductor packages that may adversely affect performance of subsequent fabrication processes, and also prevent the semiconductor packages from being damaged by unsatisfactory positioning.
REFERENCES:
patent: 5400904 (1995-03-01), Maston, III et al.
patent: 5541449 (1996-07-01), Crane, Jr. et al.
patent: 5729051 (1998-03-01), Nakamura
patent: 6116427 (2000-09-01), Wu et al.
patent: 6264037 (2001-07-01), Maston, III et al.
patent: 6559537 (2003-05-01), Bolken et al.
Chen G. F.
Jhong Jheng-Xian
Corless Peter F.
Edwards & Angell LLP
Jensen Steven M.
Meier Stephen D.
Siliconware Precision Industries Co. Ltd.
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