Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2008-05-07
2008-12-30
Phung, Anh (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185150, C365S185290
Reexamination Certificate
active
07471564
ABSTRACT:
Methods of manufacturing a nitride trapping EEPROM flash memory are described where each memory cell uses Si-Fin to form a nitride trapping EEPROM flash cell in which the source region and drain region are undoped. Each adjacent poly-gate to a selected poly-gate in a row of nitride trapping memory cells is used to produce the inversion region that acts as a source region or a drain region for transferring of a required voltage, which conserves the density of a memory cell given that the source region and the drain region for each memory cell are not doped. The flash memory includes a plurality of polysilicon layers intersecting with a plurality of Si-Fin layers.
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Xuan et al., “FinFET Sonos Flash Memory for Embedded Applications,” IEEE 2003, pp. 26.4-1-26.4.4.
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Hsu Chia-Lun
Liu Mu-Yi
Haynes Beffel & Wolfeld LLP
Macronix International Co. Ltd.
Nguyen Hien N
Phung Anh
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