Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2007-11-01
2010-06-22
Ho, Hoai V (Department: 2827)
Static information storage and retrieval
Floating gate
Multiple values
C365S185050, C365S185280
Reexamination Certificate
active
07742336
ABSTRACT:
A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.
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Ogura Nori
Ogura Seiki
Ogura Tomoko
Ackerman Stephen B.
Gumbo Logic, Inc.
Ho Hoai V
Saile Ackerman LLC
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