Transverse junction field effect transistor

Details Transverse junction field effect transistor Transverse junction field effect transistor

2002-06-19

2004-11-23

Tran, Minhloan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

C257S077000, C257S134000, C257S328000, C257S329000

Reexamination Certificate

active

06822275

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a transverse junction field effect transistor (JFET: Junction Field Effect Transistor), and more specifically, it relates to a transverse junction field effect transistor employed as a power transistor for electric power.
BACKGROUND TECHNIQUE
A junction field effect transistor (JFET) applies a reverse bias voltage from a gate electrode to a p-n junction provided on a side portion of a channel region passing carriers therethrough, thereby spreading a depletion layer from the p-n junction to the channel region and controlling the conductance of the channel region for performing operation such as switching. In a “transverse” JFET, carriers move in parallel with an element face in the channel region. While the carriers for the channel may be either electrons (n-type) or holes (p-type), mobility of electrons is higher as compared with holes in SiC to which the present invention is directed, and hence the channel region is generally formed by an n-type impurity region. For the purpose of convenience, therefore, it is assumed that the carriers for the channel are electrons and hence the channel region is an n-type impurity region in the following description, while the channel region may alternatively be formed by a p-type impurity region, as a matter of course.
SiC, having large mobility of carriers similarly to Si as described above, a high saturation drift velocity similarly to GaAs and a high withstand voltage, is subjected to study for application to a high-speed switching element or a high-power element. Crystal structures of SiC include a hexagonal closest packing structure and a cubic closest packing structure, while the hexagonal closest packing structure includes a number of structures having different cycle periods of layers and at least 100 polytypes are known. Representative polytypes are 3C, 4H, 6H and the like. C means cubic and H means hexagonal, while the prefixed numerals express cycle periods. Only 3C is cubic and referred to as &bgr;—SiC, and the remaining polytypes are referred to as &agr;—SiC as a whole. In the following description, only 6H or 4H of &agr;—SiC is solely employed.
FIG. 34
is a sectional view showing an exemplary JFET employing SiC (U.S. Pat. No. 5,264,713 granted to John W. Palmour et al.). Referring to
FIG. 34
, the conductivity type of an SiC substrate
101
is preferably the p-type, to define a p-type SiC substrate. The conductivity type of an SiC film
102
formed on a partial region of the SiC substrate
101
is also preferably the p-type, to define a p-type SiC film
102
. Further, an n-type SiC film
103
is formed on this p-type SiC film
102
to include a thinned portion
111
corresponding to a channel region. An n
+
-type impurity layer
117
coming into ohmic contact with a source electrode
112
and an n
+
-type impurity layer
118
coming into ohmic contact with a drain electrode
113
are formed on the n-type SiC film
103
. A gate electrode
114
is formed on the back side of the aforementioned p-type SiC substrate
101
as a back gate
114
. Face portions excluding the aforementioned source, drain and gate electrodes are covered with protective films
126
.
In the aforementioned prior art (FIG.
34
), the conductivity type of the SiC substrate is preferably set to the p-type for the following reason: As hereinabove described, carriers for the channel region are formed by electrons (n-type), since high mobility is attained. Therefore, the n-type SiC film defines a layer including the channel region. Thus, the p-type SiC film defines a layer limiting the carriers in this n-type SiC film in the periphery. If an n-type SiC substrate is employed as the SiC substrate for forming this p-type SiC film, a reverse bias voltage is applied to the junction between the n-type SiC substrate and the p-type SiC film to result in a depletion layer when a plus potential is applied to the gate electrode. Therefore, it is necessary to evaluate and determine influence by this depletion layer. When the p-type SiC substrate is employed to the contrary, this influence by a depletion layer may not be evaluated and no reverse bias voltage may be taken into consideration in the junction of the multilayer part reaching the channel region in on-off action. When the SiC substrate of the aforementioned conductivity type is employed, therefore, a high-speed switching element for high power or the like can be obtained with carriers having high mobility by growing a depletion layer only in the channel region at need.
However, the p-type SiC substrate has higher defect density of micropipes or the like as compared with the n-type SiC substrate. Therefore, the defect density is increased also in a crystal growth layer essential in fabrication of the semiconductor element such as the JFET. Reflecting such high defect density, the JFET formed on the p-type SiC substrate exhibits a low yield for defining a JFET of complete quality, while a completed JFET exhibits a large leakage current.
In the aforementioned transverse JFET shown in
FIG. 34
, a forward bias voltage is applied to the junction between the source region
103
formed by an n-type impurity region and the p-type impurity layer
102
in an ON-state. In an OFF-state, a reverse bias voltage is applied to the aforementioned junction, and a depletion layer grows in the channel region to block the channel region. In the ON-state, the forward bias voltage is desirably applied to the junction between the source region
103
formed by an n-type impurity region and the p-type impurity layer
102
, and a current escapes from the channel region and flows into the gate electrode
114
. The current leaking from the channel region and flowing into the gate electrode
114
increases along with forward bias voltage rise and temperature rise. The current leaking from the channel region and flowing into the gate electrode exerts influence on the amplification factor, and the amplification factor is problematically lowered when this current increases.
In the transverse JFET shown in
FIG. 34
, the aforementioned p-n junction is formed on the overall face of the p-type epitaxial SiC film. As compared with the area of the part of the channel region in contact with the bottom of a trench
124
, therefore, the area of the aforementioned p-n junction between the n-type impurity region
103
and the p-type impurity region is problematically excessive. In other words, the ratio of a part not contributing to on-off action but defining the path for the aforementioned current leaking from the channel region is problematically large as compared with a small ratio of the area of the channel region performing on-off action in the p-n junction.
FIG. 35
is a schematic sectional view of another conventional transverse JFET employing SiC (P. A. Ivanov et al.: 4H—SiC Field-Effect Transistor Hetero-Epitaxially Grown on 6H—SiC Substrate by Sublimation, p. 757, Silicon Carbide and Related Materials, 1995 Conf., Kyoto, Japan). Referring to
FIG. 35
, a 4H—SiC film
109
containing Sn is hetero-epitaxially grown on a 6H—SiC substrate
101
, for defining a buffer layer
109
. An SiC film
102
containing Al serving as a p
+
-type impurity is formed on the buffer layer
109
, and an n-type SiC film
103
containing nitrogen, having a channel region
111
arranged on the central portion along with a source region
117
and a drain region
118
located on both sides thereof is formed thereon. A source electrode
112
and a drain electrode
113
are provided on upper portions of the left and right sides of the channel region, and gate electrodes
114
are formed on portions downward beyond the source and drain electrodes through trenches
115
. Ni films defining underlayer films
120
and Al films defining upper films
121
are formed as the electrodes
114
. When this transverse JFET is employed, a JFET having high drift mobility of electrons and extremely high mobility of electrons can be formed.
However, the JFET shown in
FIG. 35
has the following problems:
(a) The JFET is insuffic

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