Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
2002-08-16
2004-06-22
Thai, Luan (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With structure for mounting semiconductor chip to lead frame
C257S666000, C257S784000
Reexamination Certificate
active
06753598
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices in general and, more particularly, to the configuration of Leads-Over-Chip (LOC) semiconductor devices.
2. State of the Art
Modern packaged integrated circuits (IC) comprise one or more encapsulated semiconductor devices, dice or chips within a protective “package” of plastic, ceramic or other moldable material. Typically, a large number of dice are formed from a wafer made from a semiconductor material such as silicon, germanium or gallium arsenide. Microscopic circuits are formed on a surface of each semiconductor die by photolithographic techniques and typically attached to a lead frame with conductive wires. More particularly, a plurality of leads of the lead frame is connected to bond pads on the semiconductor die or dice, enabling the dice to be electrically interconnected to an external electrical host apparatus, typically mounted on a circuit board.
Early semiconductor devices used relatively large semiconductor dice with peripheral bond pads. Off-die leads were wire-bonded to the peripheral bond pads. With the later introduction of Leads-Over-Chip (LOC) technology, the package size using large semiconductor dice could be reduced. This was accomplished by using centrally positioned conductive bond pads on the semiconductor die and insulatively bonding the inner leads to the semiconductor die surface close to the bond pads for wire connection. Thus, the semiconductor die and lead frame were more intimately joined, and the outer leads could be formed close to or adjacent the semiconductor dice.
In early LOC devices, the semiconductor dice were relatively large, consuming most of the package space. The number of leads attached to the semiconductor dice was also limited. Thus, wide and short leads which closely approached the bond pads on the active surface of the semiconductor die were used. The resulting wire-bonds were short and the inductance between the semiconductor die and the host apparatus was low. Examples of such are found in U.S. Pat. No. 5,227,661 of Heinen, U.S. Pat. No. 5,233,220 of Lamson et al., U.S. Pat. No. 5,252,853 of Michii, U.S. Pat. No. 5,331,200 of Teo et al., U.S. Pat. No. 5,418,189 of Heinen, and U.S. Pat. No. 5,466,888 of Beng et al.
In later generation IC devices, the semiconductor dice have become progressively smaller while the numbers of leads of the lead frame have typically increased. As a result, the inner leads of the lead frame of such devices must of necessity be reduced in lead width and pitch, both of which increase the lead inductance and slow the speed of the device. In addition, a minimum lead width is required for high-quality wire-bonding. The high density of wire connections typically makes wire-bonding more difficult and increases the frequency of bond failures. Furthermore, with very small semiconductor dice, the very fine wires may be very long, resulting in “wire sweep,” sagging, short circuiting and bond failure during encapsulation of the semiconductor die and lead frame. For a very small semiconductor die, fitting all of the inner leads of the lead frame onto the active surface of the semiconductor die is generally not possible, given the present size and space limitations. Even conventional off-die wire-bonding is very difficult or not possible in production scale.
High inductance and reduced speed limit the usefulness of packaged semiconductor dice with long, narrow leads, and shorting or destruction of the wire-bonds will make the device useless.
The required spacing, width and length of leads and wires have become serious limitations in further miniaturization of semiconductor dice and their packages. While complex integrated circuits may be formed in very small semiconductor dice, connecting such a die or dice to leads for interconnection to a host apparatus while maintaining the semiconductor die characterization is very difficult.
There have been various attempts at overcoming the high inductance or interactive conductance effects of small semiconductor die devices. For example, in U.S. Pat. No. 5,521,426 of Russell is disclosed a lead-on-chip (LOC) device with long, narrow leads. In order to decrease the capacitance between the leads and the die and increase lead strength, the leads are stamped or rolled to have a non-rectangular cross-section such as a “U” configuration. Thus, the strength of the lead and its cross-sectional area are increased, resulting in less lead sag and lowered capacitative interaction. However, the cost of producing such leads is considerable, and the package thickness is increased. Furthermore, the method does not increase the size of wire-bonding areas on the lead fingers, and the wire-bonding operation is no easier.
In U.S. Pat. No. 4,984,059 of Kubota et al., a semiconductor device is shown with the long sides of the die parallel to the rows of outer lead ends, i.e. in a non-transverse configuration. The device has a very limited number of pins.
U.S. Pat. No. 5,218,229 of Farnworth discloses a lead frame design in which a semiconductor die with opposing rows of peripheral bond pads on the active surface of the die is positioned for off-die wire attachment. The rows of bond pads are perpendicular to the two rows of outer lead ends.
U.S. Pat. No. 4,989,068 of Yasuhara et al. shows a semiconductor device in which all leads are LOC leads between two rows of peripheral bond pads.
None of the above prior art documents discloses a high-speed semiconductor device having a large number of bond pads on a small die, whereby the lead inductance is minimized and wire-bonding operations are enhanced. The need exists for such a device.
SUMMARY OF THE INVENTION
In the invention, an improved device uses a hybrid lead frame/semiconductor die configuration wherein a semiconductor die having peripheral or near-peripheral bond pads is positioned in a transverse direction relative to the lead frame. The inner leads, i.e. lead fingers, include a set of lead fingers configured to be wire-bonded off-die to peripheral bond pads and another set of lead fingers configured for lead-over-chip (LOC) attachment inside of the row(s) of wire-bond pads. The resulting device has lead fingers of increased width and pitch.
As a result of this hybrid lead frame/semiconductor die configuration, (a) lead inductance is decreased to ensure signal integrity, (b) wire-bonding is faster, easier, and more accurate, (c) wire-bond integrity and reliability are enhanced, (d) the shorter wires avoid problems with “wire sweep,” (e) the lead frame is stronger and less subject to damage in handling, (f) signal integrity is increased, (g) the speed grade of the device is increased because of the reduced lead/wire inductance, and (h) a higher value product may be manufactured at lower cost.
REFERENCES:
patent: 4033844 (1977-07-01), Pantiga et al.
patent: 4089733 (1978-05-01), Zimmerman
patent: 4279682 (1981-07-01), Hamagami et al.
patent: 4801999 (1989-01-01), Hayward et al.
patent: 4835120 (1989-05-01), Mallik et al.
patent: 4862245 (1989-08-01), Pashby et al.
patent: 4891687 (1990-01-01), Mallik et al.
patent: 4894752 (1990-01-01), Murata et al.
patent: 4937656 (1990-06-01), Kohara
patent: 4943843 (1990-07-01), Okinaga et al.
patent: 4984059 (1991-01-01), Kubota et al.
patent: 4989068 (1991-01-01), Yasuhara et al.
patent: 5126821 (1992-06-01), Okinaga et al.
patent: 5140404 (1992-08-01), Fogal et al.
patent: 5142450 (1992-08-01), Olson et al.
patent: 5184208 (1993-02-01), Sakuta et al.
patent: 5218229 (1993-06-01), Farnworth
patent: 5227661 (1993-07-01), Heinen
patent: 5227662 (1993-07-01), Ohno et al.
patent: 5229639 (1993-07-01), Hansen et al.
patent: 5231755 (1993-08-01), Emanuel
patent: 5233220 (1993-08-01), Lamson et al.
patent: 5234866 (1993-08-01), Okinaga et al.
patent: 5252853 (1993-10-01), Michii
patent: 5286679 (1994-02-01), Farnworth et al.
patent: 5304842 (1994-04-01), Farnworth et al.
patent: 5331200 (1994-07-01), Teo et al.
patent: 5331201 (1994-07-01), Nishino
patent: 5352633 (1994-10-01), Abbott
patent: 5418189
Micro)n Technology, Inc.
Thai Luan
TraskBritt
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