Transport stream decoder and digital broadcasting receiving...

Television – Bandwidth reduction system – Data rate reduction

Reexamination Certificate

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Details

C348S500000, C348S425400, C348S554000, C348S555000, C348S512000, C370S314000

Reexamination Certificate

active

06922213

ABSTRACT:
In a transport stream decoder, a plurality of synchronization establishment circuits receive a plurality of different transport streams and a plurality of input clocks corresponding thereto, to establish synchronization between the transport streams and the input clocks. A multiple TS time-division multiplexing circuit receives outputs of two FIFO memories, converts a plurality of transport stream signals into time-division multiplexing signals synchronizing with an internal processing clock, and provides an addition of a TS identification signal indicating which one of the transport streams corresponds to each time-division multiplexing signal. Therefore, a TS decoder with suppressed circuit scale can be provided even when different types of transport streams are handled.

REFERENCES:
patent: 5583562 (1996-12-01), Birch et al.
patent: 5588025 (1996-12-01), Strolle et al.
patent: 6285408 (2001-09-01), Choi et al.
patent: 6377613 (2002-04-01), Kawabe et al.
patent: 6504855 (2003-01-01), Matsunaga
patent: 6515987 (2003-02-01), Carrozza et al.
patent: 6804259 (2004-10-01), Onagawa
patent: 2000-115739 (2000-04-01), None
patent: WO99/60736 (1999-11-01), None
Office Action dated Nov. 4, 2003 with English Translation.

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