Transparent system interrupts with automated halt state restart

Details Transparent system interrupts with automated halt state restart Transparent system interrupts with automated halt state restart

1991-08-30

1994-03-01

Heckler, Thomas M.

Boots, shoes, and leggings

364DIG1, 3642808, 3642614, 3642632, G06F 946

Patent

active

052916049

ABSTRACT:
A dedicated memory area is provided on a microprocessor system for storing a customizable system interrupt service routine, processor state data at the time of interruption and a halt indicator indicating the CPU was interrupted from a halt state. The dedicated memory area is normally not mapped as part of the main memory space, thereby keep it inaccessible to the operating system and applications. An unmaskable system supervisor interrupt having higher priority than all other maskable and unmaskable interrupts is added to the CPU interrupts. The halt state indicator is set by the added interrupt of the CPU is in a halt state at the time of interruption. A RESUME instruction is added to the CPU instructions to provide recovery of the CPU to the state before it was interrupted. The Halt instruction is re-executed by the RESUME instruction if the halt state indicator remains set at the time of restoration. As a result, a system integrator or OEM may provide transparent system level interrupts with automated halt state restart that will operate reliably in any operating environment, and be relieved of the burden of managing halt state restart.

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07/886,965 Method & Apparatus For Servicing Transparent System Interrupts and Reducing Interrupt Latency, May 21, 1992.

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