Transparent multi-mode PAM interface

Pulse or digital communications – Pulse amplitude modulation

Reexamination Certificate

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Details

C375S286000, C375S259000

Reexamination Certificate

active

10805413

ABSTRACT:
Provided are a method and apparatus for high-speed, multi-mode PAM symbol transmission. A multi-mode PAM output driver drives one or more symbols, the number of levels used in the PAM modulation of the one or more symbols depending on the state of a PAM mode signal. Additionally, the one or more symbols are driven at a symbol rate, the symbol rate selected in accordance with the PAM mode signal so that a data rate of the driven symbols is constant with respect to changes in the state of the PAM mode signal. Further provided are methods for determining the optimal number of PAM levels for symbol transmission and reception in a given physical environment.

REFERENCES:
patent: 7072415 (2006-07-01), Zerbe et al.
patent: 7124221 (2006-10-01), Zerbe et al.
patent: 2002/0075968 (2002-06-01), Zerbe et al.
patent: 0 407 031 (1991-01-01), None
patent: WO 01/58035 (2001-08-01), None
J. Zerbe, C. Werner, V. Stojanovic, F. Chen, J. Wei, G. Tsang, D. Kim, W. Stonecypher, A. Ho, T. Thrush, R. Kollipara, G-J. Yeh, M. Hororwitz, K. Donnelly Equalization and Clock Recovery for a 2.5—10Gb/s 2-PAM/4-PAM Backplane Transceiver Cell, IEEE International Solid-State Circuits Conference, Feb. 2003,.
International Search Report re: International Application No. PCT/US2004/035990, International Filing Date Oct. 26, 2004.
Zerbe J. et al., “Equalization and Clock Recovery for a 2.5—10Gb/s 2-PAM/4-PAM Backplane Transceiver Cell,”IEEE International Solid-State Circuits Conference, Feb. 2003, San Francisco.

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