Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2001-06-02
2004-05-11
Mai, Tan V. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S290000
Reexamination Certificate
active
06735607
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to the field of mathematical interpolators. More specifically, the present invention relates to the use of mathematical interpolators in conjunction with computer memories.
BACKGROUND OF THE INVENTION
A computer memory often contains a table of continuous and/or cyclic data. Such data tables are typically used to provide mathematical functions, such as trigonometric and logarithmic functions. A typical such table may contain sine and/or cosine data for a fast Fourier transform function.
In order to realize a desired degree of accuracy, such tables tend to be large. Large tables require extensive use of computer memory. This increases the on-chip real estate and power consumption, thereby increasing the overall cost of the tables.
Some method is often used to reduce the overall size of the table and of the computer memory in which it is contained. The approach most often taken is that of using a smaller table in conjunction with an interpolator to approximate inter-tabular values.
One problem of conventional table-plus-interpolator schemes is that two sequential data-value accesses need be performed in order to obtain data values above and below the desired value. The interpolator then may interpolate the “correct” value between these two values.
Since the accessing computer must perform two accesses, such double-access schemes are non-transparent. That is, the computer is obliged to recognize the special nature of the table-plus-interpolator circuitry. This recognition is usually made in software.
The replacement of a large table with a smaller table plus an interpolator typically cannot be accomplished without an alteration of the software in order to accomplish the two sequential memory accesses. This inhibits the use of software intended for use with a single large table, thereby limiting the use of table-plus-interpolator schemes.
SUMMARY OF THE INVENTION
Accordingly, an advantage of the present invention is provided by a transparent data access and interpolation apparatus and method therefor.
Another advantage of the present invention is provided by a data access apparatus and method that are transparent to the accessing processor.
Another advantage of the present invention is provided by a data access apparatus and method that are usable with pre-existing software.
Another advantage of the present invention is provided by a data access apparatus and method that obtain two values for interpolation in a single access.
Another advantage of the present invention is provided by a data access and interpolation apparatus that significantly reduces on-chip memory area.
Another advantage of the present invention is provided by a data access and interpolation method that reduces power consumption during access.
The above and other advantages of the present invention are carried out in one form by a method of accessing and interpolating data, wherein the method incorporates producing first and second address portions, generating a plurality of data values of a function, storing a first half of the data values in a first table, storing a second half of the data values in a second table, accessing one of the data values in each of the first and second tables substantially simultaneously in response to said the address portion, and determining an output data value greater than or equal to one of the accessed data values in response to the second address portion.
The above and other advantages of the present invention are carried out in another form by an apparatus for accessing and interpolating data within a set of data values, the apparatus incorporating a first memory circuit containing a first table having a first half of the set of data values and configured to output a first table data value in response to a first address portion, a second memory circuit containing a second table having a second half of the set of data values and configured to output a second table data value in response to said first address portion, a routing circuit coupled to the first and second memories and configured to output a first-indexed data value and a second-indexed data value in response to the first and second table data values, and an interpolation circuit coupled to the routing circuit and configured to produce an output data value that combines the first-indexed data value and the second-indexed data value in response to a second address portion.
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Lockheed Martin Corporation
Mai Tan V.
Meschkow & Gresham P.L.C.
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