Pulse or digital communications – Cable systems and components
Reexamination Certificate
1998-06-03
2001-10-09
Vo, Don N. (Department: 2631)
Pulse or digital communications
Cable systems and components
Reexamination Certificate
active
06301305
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a transmitting apparatus for outputting a signal of binary levels over a communication line or the like.
2. Description of the Background Art
In Japanese Patent Laid-open No. Hei 5-292101, there is proposed a communication apparatus in which signals are exchanged among a plurality of communication units through a communication line. Each communication unit includes a transmitting circuit for alternately generating a high level signal or a low-level signal and for outputting the generated signal to the communication line. Each communication unit further includes a transmission control circuit for inputting a control signal to the transmitting circuit so that the transmitting circuit outputs the high-level signal or the low-level signal.
In Japanese Patent Laid-open No. Hei 5-292101, the communication apparatus is adapted to reduce the effect of stray capacitance between the communication line and ground which slows down communication, and hence to improve communication speed. The transmitting circuit includes a timing circuit for outputting a timing signal for a predetermined period of time after inversion of the level of the control signal from a first level to a second level, a first transistor responsive to the timing signal for outputting either of the high level signal and the low level signal, and a second transistor responsive to the inversion of the level of the control signal from the second level to the first level for outputting a signal at the other level to the communication line.
A further conventional type of transmitting apparatus is the so-called totem pole type in which a first transistor for outputting a high-level signal to a communication line and a second transistor for outputting a low-level signal to the communication line are connected in series and interposed between power source terminals.
FIG. 6
is a circuit configuration diagram showing an example of a conventional totem pole type transmitting apparatus.
FIG. 6
illustrates transmitting apparatus
101
including a non-inverting signal output terminal
103
for outputting a signal having a same logical level as the logical level of transmitted data supplied to the data input terminal
102
and an inverting signal output terminal
104
for outputting a signal having a logical level obtained by reversing the logical level of the transmitted data supplied to the data input terminal
102
. Transmitting apparatus
101
further includes an invertor (logically inverting circuit)
105
for inverting the logical level of the transmitted data supplied to the data input terminal
102
and two output circuits
106
and
107
.
Output circuit
106
includes a PNP transistor Q
1
, an NPN transistor Q
2
, a P-channel enhancement field effect transistor Q
3
, an N-channel enhancement field effect transistor Q
4
, and the corresponding peripheral circuits for each of the respective transistors. The emitter of PNP transistor Q
1
is connected to a positive power source V+ and the collector of PNP transistor Q
1
is connected to the non-inverting output terminal
103
. The base of PNP transistor Q
1
is connected to the output terminal of invertor
105
through base resistor R
1
. The emitter of NPN transistor Q
2
is connected to ground (or a negative power source) and the collector of NPN transistor Q
2
is connected to non-inverting output terminal
103
. The base of NPN transistor Q
2
is connected to the output terminal of invertor
105
through base resistor R
3
. Non-inverting output terminal
103
is connected to positive power source V+ through pull-up resistor R
5
. When PNP transistor Q
1
and NPN transistor Q
2
are both in an OFF state (idle state), the logical level of non-inverting output terminal
103
is held at a HIGH level by means of pull-up resistor R
5
.
Output circuit
107
is substantially the same as output circuit
106
described above except that output terminal
104
is connected to ground through resistor R
10
. Also, there is no invertor inserted between the base inputs of transistors Q
5
and Q
6
and data input terminal
102
in output circuit
107
. Operation of transmitting apparatus
101
will be described as follows.
Output circuit
106
is adapted such that the base currents of PNP transistor Q
1
and NPN transistor Q
2
are controlled in accordance with the output of invertor
105
such that either of transistors Q
1
and Q
2
are turned on based on the output of invertor
105
. When the logical level of transmitted data supplied to data input terminal
102
is HIGH, the output of invertor
105
is brought to a LOW level. When the output of invertor
105
is LOW, no base current is supplied to NPN transistor Q
2
and NPN transistor Q
2
is thus brought to an OFF state. Meanwhile, since a base current is not supplied to PNP transistor Q
1
through base resistor R
1
in this case, PNP transistor Q
1
is maintained in an ON state. Thereby, the output of the non-inverting output terminal
103
is brought to a HIGH level.
When the logical level of the transmitted data supplied to data input terminal
102
is LOW, the output of the invertor
105
is brought to a HIGH level. When the output of invertor
105
is HIGH, a base current is supplied to NPN transistor Q
2
through base resistor R
3
and NPN transistor Q
2
is brought to an ON state. At the same time, PNP transistor Q
1
is brought to an OFF state. Thereby, the output of non-inverting output terminal
103
is brought to a LOW level.
In bipolar transistors such as PNP transistors and NPN transistors, even when the supply of base current is cut off, a time delay is produced until the collector current is cut off by the effect of electric charge stored in the base region and the like. In order to shorten the cut-off delay time (turnoff time), conventional transmitting apparatus
101
includes a field effect transistor between the base and the emitter of each transistor. By turning the field effect transistor on to short-circuit the base with the emitter through a low impedance, charge on the base is forcibly discharged. By forcibly discharging the charge stored on the base, cut-off delay time (turn off time) can be shortened. This operation will be described as follows.
When the logical level of the transmitted data supplied to data input terminal
102
is HIGH, then P-channel enhancement field effect transistor Q
3
is in an OFF state and PNP transistor Q
1
is brought to an ON state by the LOW level output of invertor
105
. When the logical level of the transmitted data supplied to data input terminal
102
is changed from HIGH level to LOW level, P-channel enhancement field effect transistor Q
3
is brought to an ON state. By turning on P-channel enhancement field effect transistor Q
3
, the charge stored on the base of PNP transistor Q
1
is forcibly discharged. Thereby, the cut-off delay time (turn off time) of PNP transistor Q
1
is shortened.
On the other hand, when the logical level of the transmitted data supplied to data input terminal
102
is LOW, N-channel enhancement field effect transistor Q
4
is in an OFF state and NPN transistor Q
2
is brought to an ON state by the HIGH level output of invertor
105
. When the logical level of the transmitted data supplied to data input terminal
102
is changed from LOW level to HIGH level, N-channel enhancement field effect transistor Q
4
is brought to an ON state. By turning on N-channel enhancement field effect transistor Q
4
, the charge stored on the base of NPN transistor Q
2
is forcibly discharged. Thereby, the cut-off delay time (turn off time) of NPN transistor Q
2
is shortened.
Since conventional transmitting apparatus
101
of
FIG. 6
employs field effect transistors for shortening the cut-off delay time (turn off time) of the bipolar transistors, the number of discrete components constituting each of output circuits
106
and
107
is increased. It is therefore considered advantageous to provide circuits for shortening cut-off delay time (turn off time) of bipolar t
Ohuchi Katsuhiro
Sato Morio
Birch & Stewart Kolasch & Birch, LLP
Honda Giken Kogyo Kabushiki Kaisha
Vo Don N.
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