Transmitting and receiving apparatus and method including punctu

Details Transmitting and receiving apparatus and method including punctu Transmitting and receiving apparatus and method including punctu

1993-05-24

1995-08-01

Coles, Sr., Edward L.

Pulse or digital communications

Systems using alternating or pulsating current

375340, 371 43, H04L 2700

Patent

active

054385903

ABSTRACT:
Digital data are communicated from a transmitter to a terrestrial receiver by encoding the data into first and second 1/2 rate convolutional encoded signals during different periods. During the different periods, the convolutional signals are encoded into first and second forward error correction convolutional encoded signals having 2/3 and 6/7 punctured codes transmitted to the receiver via a satellite. Power emitted from the satellite during the first period is 3 db lower than that emitted during the second period. An antenna dish having a diameter no greater than about 1 meter is at the receiver responsive to both signals emitted from the satellite. The encoded signals include sequential bits P.sub.1 (0), P.sub.1 (1), etc. and P.sub.2 (0), P.sub.2 (1), etc. At the 2/3 rate, parallel punctured bit streams respectively including sequential bits P.sub.1 (0), P.sub.2 (1), P.sub.2 (2), P.sub.1 (4) and P.sub.2 (0), P.sub.1 (2), P.sub.2 (3), P.sub.2 (4) are derived. At the 6/7 rate, the punctured bit streams are respectively P.sub.1 (0), P.sub.2 (1), P.sub.1 (3), P.sub.1 (5), P.sub.2 (6), P.sub.2 (8), P.sub.2 (10) and P.sub.2 (0), P.sub.2 (2), P.sub.2 (4), P.sub.1 (6), P.sub.2 (7), P.sub.1 (9), P.sub.1 (11). Simultaneously derived bits of the parallel punctured bit streams simultaneously QPSK modulate a carrier. A punctured clock is combined with the serial signal to derive a pair of wavetrains G1 and G2 including the I and Q channel sequential bits and dummy bits inserted into the serial signal. The receiver responds to the QPSK carrier to derive a serial signal having sequential bits so channel I and Q sequential bits I(0), I(1), I(2) etc. and Q(0), Q(1), Q(2) etc. at the same time slots t.sub.k, t.sub.k+1, t.sub.k+2 are sequentially derived as I(0), Q(0), I(1), Q(1), I( 2), Q(2) etc.

REFERENCES:
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patent: 5233630 (1993-08-01), Wolf
patent: 5295142 (1994-03-01), Hatakeyama
Yasuda et al, "Development of Variable-Rate Viterbi Decoder and Its Performance Characteristics," Sixth International Conference on Digital Satelite Communications, Phoenix, Ariz., Sep. 19-23, 1983.
Qualcomm, Incorporated, "Q1650, K=7 Multi-Code Rate Viterbi Decoder, 2.5, 10, 25 Mbps Data Rates", Technical Data Sheet.

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