Transmitter with multiple phase locked loops

Details Transmitter with multiple phase locked loops Transmitter with multiple phase locked loops

2008-08-27

2010-10-26

Chang, Joseph (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural oscillators controlled

C331S049000, C331S016000, C327S147000, C327S156000

Reexamination Certificate

active

07821343

ABSTRACT:
A transmitter that includes a first phase locked loop (PLL) and a second PLL coupled to the first PLL is described. In one implementation, the first PLL is an inductance-capacitance (LC) type PLL and the second PLL is a ring type PLL. Also, in one embodiment, the transmitter further includes a PLL selection multiplexer coupled to the first and second PLLs, where the PLL selection multiplexer receives an output of the first PLL and an output of the second PLL and outputs either the output of the first PLL or the output of the second PLL. In one implementation, a control signal for controlling selection by the PLL selection multiplexer is programmable at runtime. In one implementation, the transmitter of the present invention further includes a clock generation block coupled to the PLL selection multiplexer, a serializer block coupled to the clock generation block and a transmit driver block coupled to the serializer block. In one embodiment, the transmit driver block includes only one post-tap pre-driver and only one main-tap pre-driver. The transmitter of the present invention is capable of operating in a wide range mode or a low jitter mode by selecting the appropriate PLL. In wide range mode, a wider frequency range is desirable. On the other hand, in low jitter mode, a low jitter is desirable.

REFERENCES:
patent: 7449961 (2008-11-01), Sai et al.
patent: 7539278 (2009-05-01), Shumarayev et al.
patent: 7589597 (2009-09-01), Chang et al.
patent: 7602253 (2009-10-01), Kim et al.
patent: 7602254 (2009-10-01), Sandner et al.

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