Coded data generation or conversion – Digital code to digital code converters – Parallel to serial
Reexamination Certificate
2002-01-09
2003-08-26
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Parallel to serial
C327S156000
Reexamination Certificate
active
06611218
ABSTRACT:
BACKGROUND
Modern digital systems represent digital data either in series (i.e., as a series of bits) or in parallel (i.e., as a transmitting one or more bytes simultaneously using multiple data lines). While it is generally easier to store and manipulate data in parallel, it is often beneficial to transmit data in series. Many systems therefore employ parallel-to-serial converters.
FIG. 1
(prior art) depicts a parallel-to-serial converter
100
that serializes ten-bit words presented in parallel on data lines D<9:0>. Converter
100
includes a parallel shifter
105
, which in turn includes a pair of five-bit shift registers
110
and
115
. Each shift register
110
and
115
connects to one of a pair of complementary clocks C
EV
and C
OD
. Designations C
EV
and C
OD
stand for “clock even” and “clock odd,” respectively, because even data bits are presented on an output terminal D
OUT
when C
EV
is high and odd data bits are presented on output terminal D
OUT
when C
OD
is high.
Every fifth rising edge of clock C
EV
, register
110
stores the even-numbered data bits D<8,6,4,2,0> presented on bus D<9:0> and register
115
stores the odd-numbered data bits D<9,7,5,3,1> presented on the same bus. Each of registers
110
and
115
then present their respective data one bit at a time, so that both odd and even data bits are presented alternately to a data combiner
120
. Data combiner
120
alternately gates the odd and even data bits presented on respective data terminals D
OD
and D
EV
to produce a serialized version of the data produced by shifter
105
.
If manufactured using commonly available CMOS processes, converter
100
can perform with clock frequencies as high as about 2 GHz. Unfortunately, modern high-speed digital communication systems transmit serial data in the 10 Gb/s range. The frequency response of converter
100
is insufficient to meet the needs of some modern systems. More exotic processes, such as those employing silicon germanium or gallium arsenide, provide improved high-frequency response; unfortunately, this improvement comes at considerable expense.
SUMMARY
The present invention is directed top parallel-to-serial converters capable of operating at speed sufficient to meet the needs of modern communication systems without consuming excessive power or requiring complex and expensive fabrication technologies. Converters in accordance with the invention include data combiners employing current sources and differential current-steering circuits. The current-steering circuits respond to parallel data bits by producing complementary current signals representing a differential, serialized version of the parallel data bits. One embodiment of the invention includes complementary data-input transistors to expedite the data combiner's response to changes in input data.
This summary does not define the scope of the invention, which is instead defined by the appended claims.
REFERENCES:
patent: 4418418 (1983-11-01), Aoki
patent: 5162674 (1992-11-01), Allstot et al.
patent: 5909187 (1999-06-01), Ahuja
patent: 6018253 (2000-01-01), Wendell
patent: 6369626 (2002-04-01), Donnelly et al.
Gijung Ahn, Deog-Kyoon Jeong, and Gyudong Kim; “A 2-Gbaud 0.7-V Swing Voltage-Mode Driver and On-Chip Terminator for High-Speed NRZ Data Transmission”; IEEE Journal of Solid-State Circuits, vol. 35, No. 6; Jun. 2000; pp. 915-918.
Lu Jinghui
Nix Michael A.
Behiel Arthur Joseph
Wamsley Patrick
Xilinx , Inc.
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