Telecommunications – Transmitter and receiver at same station – With transmitter-receiver switching or interaction prevention
Reexamination Certificate
1998-06-17
2002-01-22
Le, Thanh Cong (Department: 2684)
Telecommunications
Transmitter and receiver at same station
With transmitter-receiver switching or interaction prevention
C455S078000, C455S129000
Reexamination Certificate
active
06341216
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a transmitter-receiver circuit and also relates to a semiconductor integrated circuit device including the transmitter-receiver circuit. More particularly, the present invention relates to transmitter-receiver circuit and semiconductor integrated circuit device suitable for a wireless communication unit using the same frequency as both transmission frequency and reception frequency.
BACKGROUND ART
In recent years, size, weight and price of various wireless communication units, e.g., portable cellular phone units for radio communication, have been drastically reduced, and the number of users thereof has been rapidly increasing. In conventional communication systems, a system configuration requiring distinct frequencies for transmission and reception has been adopted so far. On the other hand, in order to satisfy the needs of an even larger number of users, digital implementation has been gradually applied to these units. While two distinct frequencies per line have been required conventionally, such a digital wireless communication unit can perform transmission and reception with the same frequency by dividing transmission and reception in a time-division manner.
Even in such a wireless communication unit utilizing digital implementation, however, various circuits in a wireless circuit section, including a transmitter amplifier, a low-noise receiver amplifier and a transmission/reception mode switch for switching transmission and reception, are still implemented by conventional circuits. Thus, it is an important problem to develop downsized transmitter-receiver circuits and, in particular, semiconductor integrated circuit integrated with these circuits that are suitably applicable to brand-new digital implementation.
Also, a circuit including gallium-arsenide field effect transistors (hereinafter, simply referred to as “GaAs FETs”), having low-voltage, high-efficiency and low-noise operating characteristics and high-isolation characteristics, are often used for a transmitter amplifier, a low-noise receiver amplifier and a transmission/reception mode switch in a transmitter-receiver circuit for a wireless communication unit of a digital type.
Hereinafter, an example of a conventional transmitter-receiver circuit will be described with reference to the drawings.
FIG. 11
illustrates a configuration of a conventional digital transmitter-receiver circuit using FETS. In
FIG. 11
,
110
denotes a transmitter amplifier for amplifying an input signal to be transmitted and then outputting the amplified signal.
120
denotes a low-noise receiver amplifier for amplifying an input received signal and then outputting the amplified signal.
130
denotes a mode switch for switching transmission state and reception state in a time-division manner.
140
denotes a first matching circuit for matching the impedance of the input received signal with the input impedance of the low-noise receiver amplifier
120
.
150
denotes a second matching circuit for matching the output impedance of the transmitter amplifier
110
with predetermined impedance.
160
denotes a third matching circuit for matching the output impedance of a FET
112
on the first stage with the input impedance of a FET on the second stage.
171
denotes first coupling capacitance for ac coupling the transmitter amplifier
110
with the second matching circuit
150
.
172
denotes second coupling capacitance for ac coupling the mode switch
130
with the first matching circuit
140
.
173
denotes a first interconnection, having characteristic impedance of
500
, for connecting the mode switch
130
to the second matching circuit
150
.
174
denotes a second interconnection, having characteristic impedance of 50&OHgr;, for connecting the mode switch
130
to the first matching circuit
140
.
175
denotes a third interconnection, having characteristic impedance of 50&OHgr;, for connecting the mode switch
130
to an antenna
180
used both for transmission and reception.
In the transmitter amplifier
110
shown in
FIG. 11
,
111
denotes an input terminal, through which a signal to be transmitted is input.
112
denotes a FET on the first stage, of which the gate electrode is provided with the input signal to be transmitted and the source is grounded.
113
denotes a first power supply terminal connected to the drain electrode of the FET
112
on the first stage.
114
denotes a FET on the second stage, of which the gate electrode is provided with the signal to be transmitted via the third matching circuit
160
and the source is grounded.
115
denotes a second power supply terminal connected to the drain electrode of the FET
114
on the second stage.
116
denotes an output terminal connected to the drain electrode of the FET
114
on the second stage.
In the low-noise receiver amplifier
120
shown in
FIG. 11
,
121
denotes an input terminal, through which a received signal is input via the first matching circuit
140
.
122
denotes a low-noise FET, of which the gate electrode is provided with the received signal and the source is grounded.
123
denotes an output terminal connected to the drain electrode of the low-noise FET
122
.
In the mode switch
130
shown in
FIG. 11
,
131
denotes an input terminal on the transmission side connected to the second matching circuit
150
.
132
denotes an input/output terminal on the antenna side for outputting a signal to be transmitted, which has been amplified by the transmitter amplifier
110
and then input thereto via the second matching circuit
150
during transmission, to the antenna
180
, and for receiving the received signal that has been received by the antenna
180
during reception.
133
denotes an output terminal on the reception side, through which the received signal input from the input/output terminal
132
on the antenna side is output.
134
A denotes first switch-control-signal input terminals for controlling a first switching FET
135
and a third switching FET
137
.
134
B denotes second switch-control-signal input terminals for controlling a second switching FET
136
and a fourth switching FET
138
.
In the first matching circuit
140
shown in
FIG. 11
,
141
denotes an input terminal connected to the output terminal
133
on the reception side of the mode switch
130
via the second coupling capacitance
172
.
142
denotes an output terminal connected to the input terminal
121
of the low-noise receiver amplifier
120
.
143
denotes a first inductor, one end of which is connected to the input terminal
141
and the other end of which is grounded, for constituting the first matching circuit
140
.
144
denotes a second inductor, one end of which is connected to the input terminal
141
and the other end of which is connected to the output terminal
142
, for constituting the first matching circuit
140
.
In the second matching circuit
150
shown in
FIG. 11
,
151
denotes an input terminal connected to the output terminal
116
of the transmitter amplifier via the first coupling capacitance
171
.
152
denotes an output terminal connected to the input terminal
131
on the transmission side of the mode switch
130
.
153
denotes a first capacitor, one end of which is connected to the input terminal
151
and the other end of which is grounded, for constituting the second matching circuit
150
.
154
denotes an inductor, one end of which is connected to the input terminal
151
and the other end of which is connected to a second capacitor
155
, for constituting the second matching circuit
150
.
155
denotes the second capacitor, one end of which is connected to the inductor
154
and the other end of which is connected to the output terminal
152
, for constituting the second matching circuit
150
.
In the third matching circuit
160
shown in
FIG. 11
,
161
denotes a first capacitor, one end of which is connected to the drain electrode of the FET
112
on the first stage in the transmitter amplifier
110
and the other end of which is connected to an inductor
162
, for constituting the t
Cong Le Thanh
McDermott & Will & Emery
Nguyen Thuan T.
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